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0001 <Comment>//////////////////////////////////////////////////////////////////////</Comment><br/>
0002 <Comment>//// ////</Comment><br/>
0003 <Comment>//// OR1200's Debug Unit ////</Comment><br/>
0004 <Comment>//// ////</Comment><br/>
0005 <Comment>//// This file is part of the OpenRISC 1200 project ////</Comment><br/>
0006 <Comment>//// http://www.opencores.org/project,or1k ////</Comment><br/>
0007 <Comment>//// ////</Comment><br/>
0008 <Comment>//// Description ////</Comment><br/>
0009 <Comment>//// Basic OR1200 debug unit. ////</Comment><br/>
0010 <Comment>//// ////</Comment><br/>
0011 <Comment>//// To Do: ////</Comment><br/>
0012 <Comment>//// - make it smaller and faster ////</Comment><br/>
0013 <Comment>//// ////</Comment><br/>
0014 <Comment>//// Author(s): ////</Comment><br/>
0015 <Comment>//// - Damjan Lampret, lampret@opencores.org ////</Comment><br/>
0016 <Comment>//// ////</Comment><br/>
0017 <Comment>//////////////////////////////////////////////////////////////////////</Comment><br/>
0018 <Comment>//// ////</Comment><br/>
0019 <Comment>//// Copyright (C) 2000 Authors and OPENCORES.ORG ////</Comment><br/>
0020 <Comment>//// ////</Comment><br/>
0021 <Comment>//// This source file may be used and distributed without ////</Comment><br/>
0022 <Comment>//// restriction provided that this copyright statement is not ////</Comment><br/>
0023 <Comment>//// removed from the file and that any derivative work contains ////</Comment><br/>
0024 <Comment>//// the original copyright notice and the associated disclaimer. ////</Comment><br/>
0025 <Comment>//// ////</Comment><br/>
0026 <Comment>//// This source file is free software; you can redistribute it ////</Comment><br/>
0027 <Comment>//// and/or modify it under the terms of the GNU Lesser General ////</Comment><br/>
0028 <Comment>//// Public License as published by the Free Software Foundation; ////</Comment><br/>
0029 <Comment>//// either version 2.1 of the License, or (at your option) any ////</Comment><br/>
0030 <Comment>//// later version. ////</Comment><br/>
0031 <Comment>//// ////</Comment><br/>
0032 <Comment>//// This source is distributed in the hope that it will be ////</Comment><br/>
0033 <Comment>//// useful, but WITHOUT ANY WARRANTY; without even the implied ////</Comment><br/>
0034 <Comment>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////</Comment><br/>
0035 <Comment>//// PURPOSE. See the GNU Lesser General Public License for more ////</Comment><br/>
0036 <Comment>//// details. ////</Comment><br/>
0037 <Comment>//// ////</Comment><br/>
0038 <Comment>//// You should have received a copy of the GNU Lesser General ////</Comment><br/>
0039 <Comment>//// Public License along with this source; if not, download it ////</Comment><br/>
0040 <Comment>//// from http://www.opencores.org/lgpl.shtml ////</Comment><br/>
0041 <Comment>//// ////</Comment><br/>
0042 <Comment>//////////////////////////////////////////////////////////////////////</Comment><br/>
0043 <Comment>//</Comment><br/>
0044 <Comment>//</Comment><br/>
0045 <Comment>// $Log: or1200_du.v,v $</Comment><br/>
0046 <Comment>// Revision 2.0 2010/06/30 11:00:00 ORSoC</Comment><br/>
0047 <Comment>// Minor update: </Comment><br/>
0048 <Comment>// Bugs fixed. </Comment><br/>
0049 <Normal Text></Normal Text><br/>
0050 <Comment>// synopsys translate_off</Comment><br/>
0051 <Preprocessor>`include </Preprocessor><Prep. Lib>"timescale.v"</Prep. Lib><br/>
0052 <Comment>// synopsys translate_on</Comment><br/>
0053 <Preprocessor>`include </Preprocessor><Prep. Lib>"or1200_defines.v"</Prep. Lib><br/>
0054 <Normal Text></Normal Text><br/>
0055 <Comment>//</Comment><br/>
0056 <Comment>// Debug unit</Comment><br/>
0057 <Comment>//</Comment><br/>
0058 <Normal Text></Normal Text><br/>
0059 <Keyword>module</Keyword><Normal Text> or1200_du</Normal Text><Symbol>(</Symbol><br/>
0060 <Normal Text> </Normal Text><Comment>// RISC Internal Interface</Comment><br/>
0061 <Normal Text> clk</Normal Text><Symbol>,</Symbol><Normal Text> rst</Normal Text><Symbol>,</Symbol><br/>
0062 <Normal Text> dcpu_cycstb_i</Normal Text><Symbol>,</Symbol><Normal Text> dcpu_we_i</Normal Text><Symbol>,</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>,</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>,</Symbol><br/>
0063 <Normal Text> dcpu_dat_dc</Normal Text><Symbol>,</Symbol><Normal Text> icpu_cycstb_i</Normal Text><Symbol>,</Symbol><br/>
0064 <Normal Text> ex_freeze</Normal Text><Symbol>,</Symbol><Normal Text> branch_op</Normal Text><Symbol>,</Symbol><Normal Text> ex_insn</Normal Text><Symbol>,</Symbol><Normal Text> id_pc</Normal Text><Symbol>,</Symbol><br/>
0065 <Normal Text> spr_dat_npc</Normal Text><Symbol>,</Symbol><Normal Text> rf_dataw</Normal Text><Symbol>,</Symbol><br/>
0066 <Normal Text> du_dsr</Normal Text><Symbol>,</Symbol><Normal Text> du_dmr1</Normal Text><Symbol>,</Symbol><Normal Text> du_stall</Normal Text><Symbol>,</Symbol><Normal Text> du_addr</Normal Text><Symbol>,</Symbol><Normal Text> du_dat_i</Normal Text><Symbol>,</Symbol><Normal Text> du_dat_o</Normal Text><Symbol>,</Symbol><br/>
0067 <Normal Text> du_read</Normal Text><Symbol>,</Symbol><Normal Text> du_write</Normal Text><Symbol>,</Symbol><Normal Text> du_except_stop</Normal Text><Symbol>,</Symbol><Normal Text> du_hwbkpt</Normal Text><Symbol>,</Symbol><Normal Text> du_flush_pipe</Normal Text><Symbol>,</Symbol><br/>
0068 <Normal Text> spr_cs</Normal Text><Symbol>,</Symbol><Normal Text> spr_write</Normal Text><Symbol>,</Symbol><Normal Text> spr_addr</Normal Text><Symbol>,</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>,</Symbol><Normal Text> spr_dat_o</Normal Text><Symbol>,</Symbol><br/>
0069 <Normal Text></Normal Text><br/>
0070 <Normal Text> </Normal Text><Comment>// External Debug Interface</Comment><br/>
0071 <Normal Text> dbg_stall_i</Normal Text><Symbol>,</Symbol><Normal Text> dbg_ewt_i</Normal Text><Symbol>,</Symbol><Normal Text> dbg_lss_o</Normal Text><Symbol>,</Symbol><Normal Text> dbg_is_o</Normal Text><Symbol>,</Symbol><Normal Text> dbg_wp_o</Normal Text><Symbol>,</Symbol><Normal Text> dbg_bp_o</Normal Text><Symbol>,</Symbol><br/>
0072 <Normal Text> dbg_stb_i</Normal Text><Symbol>,</Symbol><Normal Text> dbg_we_i</Normal Text><Symbol>,</Symbol><Normal Text> dbg_adr_i</Normal Text><Symbol>,</Symbol><Normal Text> dbg_dat_i</Normal Text><Symbol>,</Symbol><Normal Text> dbg_dat_o</Normal Text><Symbol>,</Symbol><Normal Text> dbg_ack_o</Normal Text><br/>
0073 <Symbol>);</Symbol><br/>
0074 <Normal Text></Normal Text><br/>
0075 <Data Type>parameter</Data Type><Normal Text> dw </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_OPERAND_WIDTH</Preprocessor><Symbol>;</Symbol><br/>
0076 <Data Type>parameter</Data Type><Normal Text> aw </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_OPERAND_WIDTH</Preprocessor><Symbol>;</Symbol><br/>
0077 <Normal Text></Normal Text><br/>
0078 <Comment>//</Comment><br/>
0079 <Comment>// I/O</Comment><br/>
0080 <Comment>//</Comment><br/>
0081 <Normal Text></Normal Text><br/>
0082 <Comment>//</Comment><br/>
0083 <Comment>// RISC Internal Interface</Comment><br/>
0084 <Comment>//</Comment><br/>
0085 <Data Type>input</Data Type><Normal Text> clk</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// Clock</Comment><br/>
0086 <Data Type>input</Data Type><Normal Text> rst</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// Reset</Comment><br/>
0087 <Data Type>input</Data Type><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// LSU status</Comment><br/>
0088 <Data Type>input</Data Type><Normal Text> dcpu_we_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// LSU status</Comment><br/>
0089 <Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// LSU addr</Comment><br/>
0090 <Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// LSU store data</Comment><br/>
0091 <Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// LSU load data</Comment><br/>
0092 <Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_FETCHOP_WIDTH</Preprocessor><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> icpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// IFETCH unit status</Comment><br/>
0093 <Data Type>input</Data Type><Normal Text> ex_freeze</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// EX stage freeze</Comment><br/>
0094 <Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_BRANCHOP_WIDTH</Preprocessor><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> branch_op</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// Branch op</Comment><br/>
0095 <Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Normal Text>dw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> ex_insn</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// EX insn</Comment><br/>
0096 <Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> id_pc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// insn fetch EA</Comment><br/>
0097 <Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> spr_dat_npc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// Next PC (for trace)</Comment><br/>
0098 <Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> rf_dataw</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// ALU result (for trace)</Comment><br/>
0099 <Data Type>output</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DSR_WIDTH</Preprocessor><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> du_dsr</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// DSR</Comment><br/>
0100 <Data Type>output</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>24</Integer><Symbol>:</Symbol><Normal Text> </Normal Text><Integer>0</Integer><Symbol>]</Symbol><Normal Text> du_dmr1</Normal Text><Symbol>;</Symbol><br/>
0101 <Data Type>output</Data Type><Normal Text> du_stall</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// Debug Unit Stall</Comment><br/>
0102 <Data Type>output</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Normal Text>aw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> du_addr</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// Debug Unit Address</Comment><br/>
0103 <Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Normal Text>dw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> du_dat_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// Debug Unit Data In</Comment><br/>
0104 <Data Type>output</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Normal Text>dw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> du_dat_o</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// Debug Unit Data Out</Comment><br/>
0105 <Data Type>output</Data Type><Normal Text> du_read</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// Debug Unit Read Enable</Comment><br/>
0106 <Data Type>output</Data Type><Normal Text> du_write</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// Debug Unit Write Enable</Comment><br/>
0107 <Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>13</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> du_except_stop</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// Exception masked by DSR</Comment><br/>
0108 <Data Type>output</Data Type><Normal Text> du_hwbkpt</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// Cause trap exception (HW Breakpoints)</Comment><br/>
0109 <Data Type>output</Data Type><Normal Text> du_flush_pipe</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// Cause pipeline flush and pc<-npc</Comment><br/>
0110 <Data Type>input</Data Type><Normal Text> spr_cs</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// SPR Chip Select</Comment><br/>
0111 <Data Type>input</Data Type><Normal Text> spr_write</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// SPR Read/Write</Comment><br/>
0112 <Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Normal Text>aw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> spr_addr</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// SPR Address</Comment><br/>
0113 <Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Normal Text>dw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// SPR Data Input</Comment><br/>
0114 <Data Type>output</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Normal Text>dw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> spr_dat_o</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// SPR Data Output</Comment><br/>
0115 <Normal Text></Normal Text><br/>
0116 <Comment>//</Comment><br/>
0117 <Comment>// External Debug Interface</Comment><br/>
0118 <Comment>//</Comment><br/>
0119 <Data Type>input</Data Type><Normal Text> dbg_stall_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// External Stall Input</Comment><br/>
0120 <Data Type>input</Data Type><Normal Text> dbg_ewt_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// External Watchpoint Trigger Input</Comment><br/>
0121 <Data Type>output</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>3</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dbg_lss_o</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// External Load/Store Unit Status</Comment><br/>
0122 <Data Type>output</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dbg_is_o</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// External Insn Fetch Status</Comment><br/>
0123 <Data Type>output</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>10</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dbg_wp_o</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// Watchpoints Outputs</Comment><br/>
0124 <Data Type>output</Data Type><Normal Text> dbg_bp_o</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// Breakpoint Output</Comment><br/>
0125 <Data Type>input</Data Type><Normal Text> dbg_stb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// External Address/Data Strobe</Comment><br/>
0126 <Data Type>input</Data Type><Normal Text> dbg_we_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// External Write Enable</Comment><br/>
0127 <Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Normal Text>aw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dbg_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// External Address Input</Comment><br/>
0128 <Data Type>input</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Normal Text>dw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dbg_dat_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// External Data Input</Comment><br/>
0129 <Data Type>output</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Normal Text>dw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dbg_dat_o</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// External Data Output</Comment><br/>
0130 <Data Type>output</Data Type><Normal Text> dbg_ack_o</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// External Data Acknowledge (not WB compatible)</Comment><br/>
0131 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Normal Text>dw</Normal Text><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dbg_dat_o</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// External Data Output</Comment><br/>
0132 <Data Type>reg</Data Type><Normal Text> dbg_ack_o</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// External Data Acknowledge (not WB compatible)</Comment><br/>
0133 <Normal Text></Normal Text><br/>
0134 <Normal Text></Normal Text><br/>
0135 <Comment>//</Comment><br/>
0136 <Comment>// Some connections go directly from the CPU through DU to Debug I/F</Comment><br/>
0137 <Comment>//</Comment><br/>
0138 <Preprocessor>`ifdef OR1200_DU_STATUS_UNIMPLEMENTED</Preprocessor><br/>
0139 <Keyword>assign</Keyword><Normal Text> dbg_lss_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>4'b0000</Binary><Symbol>;</Symbol><br/>
0140 <Normal Text></Normal Text><br/>
0141 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dbg_is_o</Normal Text><Symbol>;</Symbol><br/>
0142 <Comment>//</Comment><br/>
0143 <Comment>// Show insn activity (temp, must be removed)</Comment><br/>
0144 <Comment>//</Comment><br/>
0145 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0146 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0147 <Normal Text> dbg_is_o </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>2'b00</Binary><Symbol>;</Symbol><br/>
0148 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(!</Symbol><Normal Text>ex_freeze </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>~((</Symbol><Normal Text>ex_insn</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>26</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_OR32_NOP</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> ex_insn</Normal Text><Symbol>[</Symbol><Integer>16</Integer><Symbol>]))</Symbol><br/>
0149 <Normal Text> dbg_is_o </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Symbol>~</Symbol><Normal Text>dbg_is_o</Normal Text><Symbol>;</Symbol><br/>
0150 <Preprocessor>`ifdef UNUSED</Preprocessor><br/>
0151 <Keyword>assign</Keyword><Normal Text> dbg_is_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>2'b00</Binary><Symbol>;</Symbol><br/>
0152 <Preprocessor>`endif</Preprocessor><br/>
0153 <Preprocessor>`else</Preprocessor><br/>
0154 <Keyword>assign</Keyword><Normal Text> dbg_lss_o </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_cycstb_i </Normal Text><Symbol>?</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Normal Text>dcpu_we_i</Normal Text><Symbol>,</Symbol><Normal Text> </Normal Text><Binary>3'b000</Binary><Symbol>}</Symbol><Normal Text> </Normal Text><Symbol>:</Symbol><Normal Text> </Normal Text><Binary>4'b0000</Binary><Symbol>;</Symbol><br/>
0155 <Keyword>assign</Keyword><Normal Text> dbg_is_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Binary>1'b0</Binary><Symbol>,</Symbol><Normal Text> icpu_cycstb_i</Normal Text><Symbol>};</Symbol><br/>
0156 <Preprocessor>`endif</Preprocessor><br/>
0157 <Keyword>assign</Keyword><Normal Text> dbg_wp_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>11'b000_0000_0000</Binary><Symbol>;</Symbol><br/>
0158 <Normal Text></Normal Text><br/>
0159 <Comment>//</Comment><br/>
0160 <Comment>// Some connections go directly from Debug I/F through DU to the CPU</Comment><br/>
0161 <Comment>//</Comment><br/>
0162 <Keyword>assign</Keyword><Normal Text> du_stall </Normal Text><Symbol>=</Symbol><Normal Text> dbg_stall_i</Normal Text><Symbol>;</Symbol><br/>
0163 <Keyword>assign</Keyword><Normal Text> du_addr </Normal Text><Symbol>=</Symbol><Normal Text> dbg_adr_i</Normal Text><Symbol>;</Symbol><br/>
0164 <Keyword>assign</Keyword><Normal Text> du_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dbg_dat_i</Normal Text><Symbol>;</Symbol><br/>
0165 <Keyword>assign</Keyword><Normal Text> du_read </Normal Text><Symbol>=</Symbol><Normal Text> dbg_stb_i </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>dbg_we_i</Normal Text><Symbol>;</Symbol><br/>
0166 <Keyword>assign</Keyword><Normal Text> du_write </Normal Text><Symbol>=</Symbol><Normal Text> dbg_stb_i </Normal Text><Symbol>&&</Symbol><Normal Text> dbg_we_i</Normal Text><Symbol>;</Symbol><br/>
0167 <Normal Text></Normal Text><br/>
0168 <Comment>//</Comment><br/>
0169 <Comment>// After a sw breakpoint, the replaced instruction need to be executed.</Comment><br/>
0170 <Comment>// We flush the entire pipeline and set the pc to the current address</Comment><br/>
0171 <Comment>// to execute the restored address.</Comment><br/>
0172 <Comment>//</Comment><br/>
0173 <Normal Text></Normal Text><br/>
0174 <Data Type>reg</Data Type><Normal Text> du_flush_pipe_r</Normal Text><Symbol>;</Symbol><br/>
0175 <Data Type>reg</Data Type><Normal Text> dbg_stall_i_r</Normal Text><Symbol>;</Symbol><br/>
0176 <Normal Text></Normal Text><br/>
0177 <Keyword>assign</Keyword><Normal Text> du_flush_pipe </Normal Text><Symbol>=</Symbol><Normal Text> du_flush_pipe_r</Normal Text><Symbol>;</Symbol><br/>
0178 <Normal Text></Normal Text><br/>
0179 <Comment>//</Comment><br/>
0180 <Comment>// Register du_flush_pipe</Comment><br/>
0181 <Comment>//</Comment><br/>
0182 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
0183 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
0184 <Normal Text> du_flush_pipe_r </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
0185 <Normal Text> </Normal Text><Keyword>end</Keyword><br/>
0186 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
0187 <Normal Text> du_flush_pipe_r </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dbg_stall_i_r </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>!</Symbol><Normal Text>dbg_stall_i </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>|</Symbol><Normal Text>du_except_stop</Normal Text><Symbol>);</Symbol><br/>
0188 <Normal Text> </Normal Text><Keyword>end</Keyword><br/>
0189 <Keyword>end</Keyword><br/>
0190 <Normal Text></Normal Text><br/>
0191 <Comment>//</Comment><br/>
0192 <Comment>// Detect dbg_stall falling edge</Comment><br/>
0193 <Comment>//</Comment><br/>
0194 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
0195 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
0196 <Normal Text> dbg_stall_i_r </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
0197 <Normal Text> </Normal Text><Keyword>end</Keyword><br/>
0198 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
0199 <Normal Text> dbg_stall_i_r </Normal Text><Symbol><=</Symbol><Normal Text> dbg_stall_i</Normal Text><Symbol>;</Symbol><br/>
0200 <Normal Text> </Normal Text><Keyword>end</Keyword><br/>
0201 <Keyword>end</Keyword><br/>
0202 <Normal Text></Normal Text><br/>
0203 <Data Type>reg</Data Type><Normal Text> dbg_ack</Normal Text><Symbol>;</Symbol><br/>
0204 <Comment>//</Comment><br/>
0205 <Comment>// Generate acknowledge -- just delay stb signal</Comment><br/>
0206 <Comment>//</Comment><br/>
0207 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
0208 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
0209 <Normal Text> dbg_ack </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
0210 <Normal Text> dbg_ack_o </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
0211 <Normal Text> </Normal Text><Keyword>end</Keyword><br/>
0212 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
0213 <Normal Text> dbg_ack </Normal Text><Symbol><=</Symbol><Normal Text> dbg_stb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// valid when du_dat_i </Comment><br/>
0214 <Normal Text> dbg_ack_o </Normal Text><Symbol><=</Symbol><Normal Text> dbg_ack </Normal Text><Symbol>&</Symbol><Normal Text> dbg_stb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// valid when dbg_dat_o </Comment><br/>
0215 <Normal Text> </Normal Text><Keyword>end</Keyword><br/>
0216 <Keyword>end</Keyword><br/>
0217 <Normal Text></Normal Text><br/>
0218 <Comment>// </Comment><br/>
0219 <Comment>// Register data output</Comment><br/>
0220 <Comment>//</Comment><br/>
0221 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk</Normal Text><Symbol>)</Symbol><br/>
0222 <Normal Text> dbg_dat_o </Normal Text><Symbol><=</Symbol><Normal Text> du_dat_i</Normal Text><Symbol>;</Symbol><br/>
0223 <Normal Text></Normal Text><br/>
0224 <Preprocessor>`ifdef OR1200_DU_IMPLEMENTED</Preprocessor><br/>
0225 <Normal Text></Normal Text><br/>
0226 <Comment>//</Comment><br/>
0227 <Comment>// Debug Mode Register 1</Comment><br/>
0228 <Comment>//</Comment><br/>
0229 <Preprocessor>`ifdef OR1200_DU_DMR1</Preprocessor><br/>
0230 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>24</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dmr1</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// DMR1 implemented</Comment><br/>
0231 <Preprocessor>`else</Preprocessor><br/>
0232 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>24</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dmr1</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// DMR1 not implemented</Comment><br/>
0233 <Preprocessor>`endif</Preprocessor><br/>
0234 <Keyword>assign</Keyword><Normal Text> du_dmr1 </Normal Text><Symbol>=</Symbol><Normal Text> dmr1</Normal Text><Symbol>;</Symbol><br/>
0235 <Normal Text></Normal Text><br/>
0236 <Comment>//</Comment><br/>
0237 <Comment>// Debug Mode Register 2</Comment><br/>
0238 <Comment>//</Comment><br/>
0239 <Preprocessor>`ifdef OR1200_DU_DMR2</Preprocessor><br/>
0240 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>23</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dmr2</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// DMR2 implemented</Comment><br/>
0241 <Preprocessor>`else</Preprocessor><br/>
0242 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>23</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dmr2</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// DMR2 not implemented</Comment><br/>
0243 <Preprocessor>`endif</Preprocessor><br/>
0244 <Normal Text></Normal Text><br/>
0245 <Comment>//</Comment><br/>
0246 <Comment>// Debug Stop Register</Comment><br/>
0247 <Comment>//</Comment><br/>
0248 <Preprocessor>`ifdef OR1200_DU_DSR</Preprocessor><br/>
0249 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DSR_WIDTH</Preprocessor><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dsr</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// DSR implemented</Comment><br/>
0250 <Preprocessor>`else</Preprocessor><br/>
0251 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DSR_WIDTH</Preprocessor><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dsr</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// DSR not implemented</Comment><br/>
0252 <Preprocessor>`endif</Preprocessor><br/>
0253 <Normal Text></Normal Text><br/>
0254 <Comment>//</Comment><br/>
0255 <Comment>// Debug Reason Register</Comment><br/>
0256 <Comment>//</Comment><br/>
0257 <Preprocessor>`ifdef OR1200_DU_DRR</Preprocessor><br/>
0258 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>13</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> drr</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// DRR implemented</Comment><br/>
0259 <Preprocessor>`else</Preprocessor><br/>
0260 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>13</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> drr</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// DRR not implemented</Comment><br/>
0261 <Preprocessor>`endif</Preprocessor><br/>
0262 <Normal Text></Normal Text><br/>
0263 <Comment>//</Comment><br/>
0264 <Comment>// Debug Value Register N</Comment><br/>
0265 <Comment>//</Comment><br/>
0266 <Preprocessor>`ifdef OR1200_DU_DVR0</Preprocessor><br/>
0267 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dvr0</Normal Text><Symbol>;</Symbol><br/>
0268 <Preprocessor>`else</Preprocessor><br/>
0269 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dvr0</Normal Text><Symbol>;</Symbol><br/>
0270 <Preprocessor>`endif</Preprocessor><br/>
0271 <Normal Text></Normal Text><br/>
0272 <Comment>//</Comment><br/>
0273 <Comment>// Debug Value Register N</Comment><br/>
0274 <Comment>//</Comment><br/>
0275 <Preprocessor>`ifdef OR1200_DU_DVR1</Preprocessor><br/>
0276 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dvr1</Normal Text><Symbol>;</Symbol><br/>
0277 <Preprocessor>`else</Preprocessor><br/>
0278 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dvr1</Normal Text><Symbol>;</Symbol><br/>
0279 <Preprocessor>`endif</Preprocessor><br/>
0280 <Normal Text></Normal Text><br/>
0281 <Comment>//</Comment><br/>
0282 <Comment>// Debug Value Register N</Comment><br/>
0283 <Comment>//</Comment><br/>
0284 <Preprocessor>`ifdef OR1200_DU_DVR2</Preprocessor><br/>
0285 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dvr2</Normal Text><Symbol>;</Symbol><br/>
0286 <Preprocessor>`else</Preprocessor><br/>
0287 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dvr2</Normal Text><Symbol>;</Symbol><br/>
0288 <Preprocessor>`endif</Preprocessor><br/>
0289 <Normal Text></Normal Text><br/>
0290 <Comment>//</Comment><br/>
0291 <Comment>// Debug Value Register N</Comment><br/>
0292 <Comment>//</Comment><br/>
0293 <Preprocessor>`ifdef OR1200_DU_DVR3</Preprocessor><br/>
0294 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dvr3</Normal Text><Symbol>;</Symbol><br/>
0295 <Preprocessor>`else</Preprocessor><br/>
0296 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dvr3</Normal Text><Symbol>;</Symbol><br/>
0297 <Preprocessor>`endif</Preprocessor><br/>
0298 <Normal Text></Normal Text><br/>
0299 <Comment>//</Comment><br/>
0300 <Comment>// Debug Value Register N</Comment><br/>
0301 <Comment>//</Comment><br/>
0302 <Preprocessor>`ifdef OR1200_DU_DVR4</Preprocessor><br/>
0303 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dvr4</Normal Text><Symbol>;</Symbol><br/>
0304 <Preprocessor>`else</Preprocessor><br/>
0305 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dvr4</Normal Text><Symbol>;</Symbol><br/>
0306 <Preprocessor>`endif</Preprocessor><br/>
0307 <Normal Text></Normal Text><br/>
0308 <Comment>//</Comment><br/>
0309 <Comment>// Debug Value Register N</Comment><br/>
0310 <Comment>//</Comment><br/>
0311 <Preprocessor>`ifdef OR1200_DU_DVR5</Preprocessor><br/>
0312 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dvr5</Normal Text><Symbol>;</Symbol><br/>
0313 <Preprocessor>`else</Preprocessor><br/>
0314 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dvr5</Normal Text><Symbol>;</Symbol><br/>
0315 <Preprocessor>`endif</Preprocessor><br/>
0316 <Normal Text></Normal Text><br/>
0317 <Comment>//</Comment><br/>
0318 <Comment>// Debug Value Register N</Comment><br/>
0319 <Comment>//</Comment><br/>
0320 <Preprocessor>`ifdef OR1200_DU_DVR6</Preprocessor><br/>
0321 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dvr6</Normal Text><Symbol>;</Symbol><br/>
0322 <Preprocessor>`else</Preprocessor><br/>
0323 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dvr6</Normal Text><Symbol>;</Symbol><br/>
0324 <Preprocessor>`endif</Preprocessor><br/>
0325 <Normal Text></Normal Text><br/>
0326 <Comment>//</Comment><br/>
0327 <Comment>// Debug Value Register N</Comment><br/>
0328 <Comment>//</Comment><br/>
0329 <Preprocessor>`ifdef OR1200_DU_DVR7</Preprocessor><br/>
0330 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dvr7</Normal Text><Symbol>;</Symbol><br/>
0331 <Preprocessor>`else</Preprocessor><br/>
0332 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dvr7</Normal Text><Symbol>;</Symbol><br/>
0333 <Preprocessor>`endif</Preprocessor><br/>
0334 <Normal Text></Normal Text><br/>
0335 <Comment>//</Comment><br/>
0336 <Comment>// Debug Control Register N</Comment><br/>
0337 <Comment>//</Comment><br/>
0338 <Preprocessor>`ifdef OR1200_DU_DCR0</Preprocessor><br/>
0339 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcr0</Normal Text><Symbol>;</Symbol><br/>
0340 <Preprocessor>`else</Preprocessor><br/>
0341 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcr0</Normal Text><Symbol>;</Symbol><br/>
0342 <Preprocessor>`endif</Preprocessor><br/>
0343 <Normal Text></Normal Text><br/>
0344 <Comment>//</Comment><br/>
0345 <Comment>// Debug Control Register N</Comment><br/>
0346 <Comment>//</Comment><br/>
0347 <Preprocessor>`ifdef OR1200_DU_DCR1</Preprocessor><br/>
0348 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcr1</Normal Text><Symbol>;</Symbol><br/>
0349 <Preprocessor>`else</Preprocessor><br/>
0350 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcr1</Normal Text><Symbol>;</Symbol><br/>
0351 <Preprocessor>`endif</Preprocessor><br/>
0352 <Normal Text></Normal Text><br/>
0353 <Comment>//</Comment><br/>
0354 <Comment>// Debug Control Register N</Comment><br/>
0355 <Comment>//</Comment><br/>
0356 <Preprocessor>`ifdef OR1200_DU_DCR2</Preprocessor><br/>
0357 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcr2</Normal Text><Symbol>;</Symbol><br/>
0358 <Preprocessor>`else</Preprocessor><br/>
0359 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcr2</Normal Text><Symbol>;</Symbol><br/>
0360 <Preprocessor>`endif</Preprocessor><br/>
0361 <Normal Text></Normal Text><br/>
0362 <Comment>//</Comment><br/>
0363 <Comment>// Debug Control Register N</Comment><br/>
0364 <Comment>//</Comment><br/>
0365 <Preprocessor>`ifdef OR1200_DU_DCR3</Preprocessor><br/>
0366 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcr3</Normal Text><Symbol>;</Symbol><br/>
0367 <Preprocessor>`else</Preprocessor><br/>
0368 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcr3</Normal Text><Symbol>;</Symbol><br/>
0369 <Preprocessor>`endif</Preprocessor><br/>
0370 <Normal Text></Normal Text><br/>
0371 <Comment>//</Comment><br/>
0372 <Comment>// Debug Control Register N</Comment><br/>
0373 <Comment>//</Comment><br/>
0374 <Preprocessor>`ifdef OR1200_DU_DCR4</Preprocessor><br/>
0375 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcr4</Normal Text><Symbol>;</Symbol><br/>
0376 <Preprocessor>`else</Preprocessor><br/>
0377 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcr4</Normal Text><Symbol>;</Symbol><br/>
0378 <Preprocessor>`endif</Preprocessor><br/>
0379 <Normal Text></Normal Text><br/>
0380 <Comment>//</Comment><br/>
0381 <Comment>// Debug Control Register N</Comment><br/>
0382 <Comment>//</Comment><br/>
0383 <Preprocessor>`ifdef OR1200_DU_DCR5</Preprocessor><br/>
0384 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcr5</Normal Text><Symbol>;</Symbol><br/>
0385 <Preprocessor>`else</Preprocessor><br/>
0386 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcr5</Normal Text><Symbol>;</Symbol><br/>
0387 <Preprocessor>`endif</Preprocessor><br/>
0388 <Normal Text></Normal Text><br/>
0389 <Comment>//</Comment><br/>
0390 <Comment>// Debug Control Register N</Comment><br/>
0391 <Comment>//</Comment><br/>
0392 <Preprocessor>`ifdef OR1200_DU_DCR6</Preprocessor><br/>
0393 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcr6</Normal Text><Symbol>;</Symbol><br/>
0394 <Preprocessor>`else</Preprocessor><br/>
0395 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcr6</Normal Text><Symbol>;</Symbol><br/>
0396 <Preprocessor>`endif</Preprocessor><br/>
0397 <Normal Text></Normal Text><br/>
0398 <Comment>//</Comment><br/>
0399 <Comment>// Debug Control Register N</Comment><br/>
0400 <Comment>//</Comment><br/>
0401 <Preprocessor>`ifdef OR1200_DU_DCR7</Preprocessor><br/>
0402 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcr7</Normal Text><Symbol>;</Symbol><br/>
0403 <Preprocessor>`else</Preprocessor><br/>
0404 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dcr7</Normal Text><Symbol>;</Symbol><br/>
0405 <Preprocessor>`endif</Preprocessor><br/>
0406 <Normal Text></Normal Text><br/>
0407 <Comment>//</Comment><br/>
0408 <Comment>// Debug Watchpoint Counter Register 0</Comment><br/>
0409 <Comment>//</Comment><br/>
0410 <Preprocessor>`ifdef OR1200_DU_DWCR0</Preprocessor><br/>
0411 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dwcr0</Normal Text><Symbol>;</Symbol><br/>
0412 <Preprocessor>`else</Preprocessor><br/>
0413 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dwcr0</Normal Text><Symbol>;</Symbol><br/>
0414 <Preprocessor>`endif</Preprocessor><br/>
0415 <Normal Text></Normal Text><br/>
0416 <Comment>//</Comment><br/>
0417 <Comment>// Debug Watchpoint Counter Register 1</Comment><br/>
0418 <Comment>//</Comment><br/>
0419 <Preprocessor>`ifdef OR1200_DU_DWCR1</Preprocessor><br/>
0420 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dwcr1</Normal Text><Symbol>;</Symbol><br/>
0421 <Preprocessor>`else</Preprocessor><br/>
0422 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> dwcr1</Normal Text><Symbol>;</Symbol><br/>
0423 <Preprocessor>`endif</Preprocessor><br/>
0424 <Normal Text></Normal Text><br/>
0425 <Comment>//</Comment><br/>
0426 <Comment>// Internal wires</Comment><br/>
0427 <Comment>//</Comment><br/>
0428 <Data Type>wire</Data Type><Normal Text> dmr1_sel</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// DMR1 select</Comment><br/>
0429 <Data Type>wire</Data Type><Normal Text> dmr2_sel</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// DMR2 select</Comment><br/>
0430 <Data Type>wire</Data Type><Normal Text> dsr_sel</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// DSR select</Comment><br/>
0431 <Data Type>wire</Data Type><Normal Text> drr_sel</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// DRR select</Comment><br/>
0432 <Data Type>wire</Data Type><Normal Text> dvr0_sel</Normal Text><Symbol>,</Symbol><br/>
0433 <Normal Text> dvr1_sel</Normal Text><Symbol>,</Symbol><br/>
0434 <Normal Text> dvr2_sel</Normal Text><Symbol>,</Symbol><br/>
0435 <Normal Text> dvr3_sel</Normal Text><Symbol>,</Symbol><br/>
0436 <Normal Text> dvr4_sel</Normal Text><Symbol>,</Symbol><br/>
0437 <Normal Text> dvr5_sel</Normal Text><Symbol>,</Symbol><br/>
0438 <Normal Text> dvr6_sel</Normal Text><Symbol>,</Symbol><br/>
0439 <Normal Text> dvr7_sel</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// DVR selects</Comment><br/>
0440 <Data Type>wire</Data Type><Normal Text> dcr0_sel</Normal Text><Symbol>,</Symbol><br/>
0441 <Normal Text> dcr1_sel</Normal Text><Symbol>,</Symbol><br/>
0442 <Normal Text> dcr2_sel</Normal Text><Symbol>,</Symbol><br/>
0443 <Normal Text> dcr3_sel</Normal Text><Symbol>,</Symbol><br/>
0444 <Normal Text> dcr4_sel</Normal Text><Symbol>,</Symbol><br/>
0445 <Normal Text> dcr5_sel</Normal Text><Symbol>,</Symbol><br/>
0446 <Normal Text> dcr6_sel</Normal Text><Symbol>,</Symbol><br/>
0447 <Normal Text> dcr7_sel</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// DCR selects</Comment><br/>
0448 <Data Type>wire</Data Type><Normal Text> dwcr0_sel</Normal Text><Symbol>,</Symbol><br/>
0449 <Normal Text> dwcr1_sel</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// DWCR selects</Comment><br/>
0450 <Data Type>reg</Data Type><Normal Text> dbg_bp_r</Normal Text><Symbol>;</Symbol><br/>
0451 <Data Type>reg</Data Type><Normal Text> ex_freeze_q</Normal Text><Symbol>;</Symbol><br/>
0452 <Preprocessor>`ifdef OR1200_DU_HWBKPTS</Preprocessor><br/>
0453 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> match_cond0_ct</Normal Text><Symbol>;</Symbol><br/>
0454 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> match_cond1_ct</Normal Text><Symbol>;</Symbol><br/>
0455 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> match_cond2_ct</Normal Text><Symbol>;</Symbol><br/>
0456 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> match_cond3_ct</Normal Text><Symbol>;</Symbol><br/>
0457 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> match_cond4_ct</Normal Text><Symbol>;</Symbol><br/>
0458 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> match_cond5_ct</Normal Text><Symbol>;</Symbol><br/>
0459 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> match_cond6_ct</Normal Text><Symbol>;</Symbol><br/>
0460 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> match_cond7_ct</Normal Text><Symbol>;</Symbol><br/>
0461 <Data Type>reg</Data Type><Normal Text> match_cond0_stb</Normal Text><Symbol>;</Symbol><br/>
0462 <Data Type>reg</Data Type><Normal Text> match_cond1_stb</Normal Text><Symbol>;</Symbol><br/>
0463 <Data Type>reg</Data Type><Normal Text> match_cond2_stb</Normal Text><Symbol>;</Symbol><br/>
0464 <Data Type>reg</Data Type><Normal Text> match_cond3_stb</Normal Text><Symbol>;</Symbol><br/>
0465 <Data Type>reg</Data Type><Normal Text> match_cond4_stb</Normal Text><Symbol>;</Symbol><br/>
0466 <Data Type>reg</Data Type><Normal Text> match_cond5_stb</Normal Text><Symbol>;</Symbol><br/>
0467 <Data Type>reg</Data Type><Normal Text> match_cond6_stb</Normal Text><Symbol>;</Symbol><br/>
0468 <Data Type>reg</Data Type><Normal Text> match_cond7_stb</Normal Text><Symbol>;</Symbol><br/>
0469 <Data Type>reg</Data Type><Normal Text> match0</Normal Text><Symbol>;</Symbol><br/>
0470 <Data Type>reg</Data Type><Normal Text> match1</Normal Text><Symbol>;</Symbol><br/>
0471 <Data Type>reg</Data Type><Normal Text> match2</Normal Text><Symbol>;</Symbol><br/>
0472 <Data Type>reg</Data Type><Normal Text> match3</Normal Text><Symbol>;</Symbol><br/>
0473 <Data Type>reg</Data Type><Normal Text> match4</Normal Text><Symbol>;</Symbol><br/>
0474 <Data Type>reg</Data Type><Normal Text> match5</Normal Text><Symbol>;</Symbol><br/>
0475 <Data Type>reg</Data Type><Normal Text> match6</Normal Text><Symbol>;</Symbol><br/>
0476 <Data Type>reg</Data Type><Normal Text> match7</Normal Text><Symbol>;</Symbol><br/>
0477 <Data Type>reg</Data Type><Normal Text> wpcntr0_match</Normal Text><Symbol>;</Symbol><br/>
0478 <Data Type>reg</Data Type><Normal Text> wpcntr1_match</Normal Text><Symbol>;</Symbol><br/>
0479 <Data Type>reg</Data Type><Normal Text> incr_wpcntr0</Normal Text><Symbol>;</Symbol><br/>
0480 <Data Type>reg</Data Type><Normal Text> incr_wpcntr1</Normal Text><Symbol>;</Symbol><br/>
0481 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>10</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> wp</Normal Text><Symbol>;</Symbol><br/>
0482 <Preprocessor>`endif</Preprocessor><br/>
0483 <Data Type>wire</Data Type><Normal Text> du_hwbkpt</Normal Text><Symbol>;</Symbol><br/>
0484 <Data Type>reg</Data Type><Normal Text> du_hwbkpt_hold</Normal Text><Symbol>;</Symbol><br/>
0485 <Preprocessor>`ifdef OR1200_DU_READREGS</Preprocessor><br/>
0486 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> spr_dat_o</Normal Text><Symbol>;</Symbol><br/>
0487 <Preprocessor>`endif</Preprocessor><br/>
0488 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>13</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> except_stop</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// Exceptions that stop because of DSR</Comment><br/>
0489 <Preprocessor>`ifdef OR1200_DU_TB_IMPLEMENTED</Preprocessor><br/>
0490 <Data Type>wire</Data Type><Normal Text> tb_enw</Normal Text><Symbol>;</Symbol><br/>
0491 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> tb_wadr</Normal Text><Symbol>;</Symbol><br/>
0492 <Data Type>reg</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> tb_timstmp</Normal Text><Symbol>;</Symbol><br/>
0493 <Preprocessor>`endif</Preprocessor><br/>
0494 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> tbia_dat_o</Normal Text><Symbol>;</Symbol><br/>
0495 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> tbim_dat_o</Normal Text><Symbol>;</Symbol><br/>
0496 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> tbar_dat_o</Normal Text><Symbol>;</Symbol><br/>
0497 <Data Type>wire</Data Type><Normal Text> </Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> tbts_dat_o</Normal Text><Symbol>;</Symbol><br/>
0498 <Normal Text></Normal Text><br/>
0499 <Comment>//</Comment><br/>
0500 <Comment>// DU registers address decoder</Comment><br/>
0501 <Comment>//</Comment><br/>
0502 <Preprocessor>`ifdef OR1200_DU_DMR1</Preprocessor><br/>
0503 <Keyword>assign</Keyword><Normal Text> dmr1_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DMR1</Preprocessor><Symbol>));</Symbol><br/>
0504 <Preprocessor>`endif</Preprocessor><br/>
0505 <Preprocessor>`ifdef OR1200_DU_DMR2</Preprocessor><br/>
0506 <Keyword>assign</Keyword><Normal Text> dmr2_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DMR2</Preprocessor><Symbol>));</Symbol><br/>
0507 <Preprocessor>`endif</Preprocessor><br/>
0508 <Preprocessor>`ifdef OR1200_DU_DSR</Preprocessor><br/>
0509 <Keyword>assign</Keyword><Normal Text> dsr_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DSR</Preprocessor><Symbol>));</Symbol><br/>
0510 <Preprocessor>`endif</Preprocessor><br/>
0511 <Preprocessor>`ifdef OR1200_DU_DRR</Preprocessor><br/>
0512 <Keyword>assign</Keyword><Normal Text> drr_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DRR</Preprocessor><Symbol>));</Symbol><br/>
0513 <Preprocessor>`endif</Preprocessor><br/>
0514 <Preprocessor>`ifdef OR1200_DU_DVR0</Preprocessor><br/>
0515 <Keyword>assign</Keyword><Normal Text> dvr0_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR0</Preprocessor><Symbol>));</Symbol><br/>
0516 <Preprocessor>`endif</Preprocessor><br/>
0517 <Preprocessor>`ifdef OR1200_DU_DVR1</Preprocessor><br/>
0518 <Keyword>assign</Keyword><Normal Text> dvr1_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR1</Preprocessor><Symbol>));</Symbol><br/>
0519 <Preprocessor>`endif</Preprocessor><br/>
0520 <Preprocessor>`ifdef OR1200_DU_DVR2</Preprocessor><br/>
0521 <Keyword>assign</Keyword><Normal Text> dvr2_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR2</Preprocessor><Symbol>));</Symbol><br/>
0522 <Preprocessor>`endif</Preprocessor><br/>
0523 <Preprocessor>`ifdef OR1200_DU_DVR3</Preprocessor><br/>
0524 <Keyword>assign</Keyword><Normal Text> dvr3_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR3</Preprocessor><Symbol>));</Symbol><br/>
0525 <Preprocessor>`endif</Preprocessor><br/>
0526 <Preprocessor>`ifdef OR1200_DU_DVR4</Preprocessor><br/>
0527 <Keyword>assign</Keyword><Normal Text> dvr4_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR4</Preprocessor><Symbol>));</Symbol><br/>
0528 <Preprocessor>`endif</Preprocessor><br/>
0529 <Preprocessor>`ifdef OR1200_DU_DVR5</Preprocessor><br/>
0530 <Keyword>assign</Keyword><Normal Text> dvr5_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR5</Preprocessor><Symbol>));</Symbol><br/>
0531 <Preprocessor>`endif</Preprocessor><br/>
0532 <Preprocessor>`ifdef OR1200_DU_DVR6</Preprocessor><br/>
0533 <Keyword>assign</Keyword><Normal Text> dvr6_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR6</Preprocessor><Symbol>));</Symbol><br/>
0534 <Preprocessor>`endif</Preprocessor><br/>
0535 <Preprocessor>`ifdef OR1200_DU_DVR7</Preprocessor><br/>
0536 <Keyword>assign</Keyword><Normal Text> dvr7_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR7</Preprocessor><Symbol>));</Symbol><br/>
0537 <Preprocessor>`endif</Preprocessor><br/>
0538 <Preprocessor>`ifdef OR1200_DU_DCR0</Preprocessor><br/>
0539 <Keyword>assign</Keyword><Normal Text> dcr0_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR0</Preprocessor><Symbol>));</Symbol><br/>
0540 <Preprocessor>`endif</Preprocessor><br/>
0541 <Preprocessor>`ifdef OR1200_DU_DCR1</Preprocessor><br/>
0542 <Keyword>assign</Keyword><Normal Text> dcr1_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR1</Preprocessor><Symbol>));</Symbol><br/>
0543 <Preprocessor>`endif</Preprocessor><br/>
0544 <Preprocessor>`ifdef OR1200_DU_DCR2</Preprocessor><br/>
0545 <Keyword>assign</Keyword><Normal Text> dcr2_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR2</Preprocessor><Symbol>));</Symbol><br/>
0546 <Preprocessor>`endif</Preprocessor><br/>
0547 <Preprocessor>`ifdef OR1200_DU_DCR3</Preprocessor><br/>
0548 <Keyword>assign</Keyword><Normal Text> dcr3_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR3</Preprocessor><Symbol>));</Symbol><br/>
0549 <Preprocessor>`endif</Preprocessor><br/>
0550 <Preprocessor>`ifdef OR1200_DU_DCR4</Preprocessor><br/>
0551 <Keyword>assign</Keyword><Normal Text> dcr4_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR4</Preprocessor><Symbol>));</Symbol><br/>
0552 <Preprocessor>`endif</Preprocessor><br/>
0553 <Preprocessor>`ifdef OR1200_DU_DCR5</Preprocessor><br/>
0554 <Keyword>assign</Keyword><Normal Text> dcr5_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR5</Preprocessor><Symbol>));</Symbol><br/>
0555 <Preprocessor>`endif</Preprocessor><br/>
0556 <Preprocessor>`ifdef OR1200_DU_DCR6</Preprocessor><br/>
0557 <Keyword>assign</Keyword><Normal Text> dcr6_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR6</Preprocessor><Symbol>));</Symbol><br/>
0558 <Preprocessor>`endif</Preprocessor><br/>
0559 <Preprocessor>`ifdef OR1200_DU_DCR7</Preprocessor><br/>
0560 <Keyword>assign</Keyword><Normal Text> dcr7_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR7</Preprocessor><Symbol>));</Symbol><br/>
0561 <Preprocessor>`endif</Preprocessor><br/>
0562 <Preprocessor>`ifdef OR1200_DU_DWCR0</Preprocessor><br/>
0563 <Keyword>assign</Keyword><Normal Text> dwcr0_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DWCR0</Preprocessor><Symbol>));</Symbol><br/>
0564 <Preprocessor>`endif</Preprocessor><br/>
0565 <Preprocessor>`ifdef OR1200_DU_DWCR1</Preprocessor><br/>
0566 <Keyword>assign</Keyword><Normal Text> dwcr1_sel </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_cs </Normal Text><Symbol>&&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DWCR1</Preprocessor><Symbol>));</Symbol><br/>
0567 <Preprocessor>`endif</Preprocessor><br/>
0568 <Normal Text></Normal Text><br/>
0569 <Comment>// Track previous ex_freeze to detect when signals are updated</Comment><br/>
0570 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk</Normal Text><Symbol>)</Symbol><br/>
0571 <Normal Text> ex_freeze_q </Normal Text><Symbol><=</Symbol><Normal Text> ex_freeze</Normal Text><Symbol>;</Symbol><br/>
0572 <Normal Text></Normal Text><br/>
0573 <Comment>//</Comment><br/>
0574 <Comment>// Decode started exception</Comment><br/>
0575 <Comment>//</Comment><br/>
0576 <Comment>// du_except_stop comes from or1200_except</Comment><br/>
0577 <Comment>// </Comment><br/>
0578 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>du_except_stop </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> ex_freeze_q</Normal Text><Symbol>)</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
0579 <Normal Text> except_stop </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>14'b00_0000_0000_0000</Binary><Symbol>;</Symbol><br/>
0580 <Normal Text> </Normal Text><Keyword>casez</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>du_except_stop</Normal Text><Symbol>)</Symbol><br/>
0581 <Normal Text> </Normal Text><Binary>14'b1</Binary><Symbol>?</Symbol><Normal Text>_</Normal Text><Symbol>????</Symbol><Normal Text>_</Normal Text><Symbol>????</Symbol><Normal Text>_</Normal Text><Symbol>????:</Symbol><br/>
0582 <Normal Text> except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_TTE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
0583 <Normal Text> </Normal Text><Binary>14'b01_</Binary><Symbol>????</Symbol><Normal Text>_</Normal Text><Symbol>????</Symbol><Normal Text>_</Normal Text><Symbol>????:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
0584 <Normal Text> except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_IE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
0585 <Normal Text> </Normal Text><Keyword>end</Keyword><br/>
0586 <Normal Text> </Normal Text><Binary>14'b00_1</Binary><Symbol>???</Symbol><Normal Text>_</Normal Text><Symbol>????</Symbol><Normal Text>_</Normal Text><Symbol>????:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
0587 <Normal Text> except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_IME</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
0588 <Normal Text> </Normal Text><Keyword>end</Keyword><br/>
0589 <Normal Text> </Normal Text><Binary>14'b00_01</Binary><Symbol>??</Symbol><Normal Text>_</Normal Text><Symbol>????</Symbol><Normal Text>_</Normal Text><Symbol>????:</Symbol><br/>
0590 <Normal Text> except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_IPFE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
0591 <Normal Text> </Normal Text><Binary>14'b00_001</Binary><Symbol>?</Symbol><Normal Text>_</Normal Text><Symbol>????</Symbol><Normal Text>_</Normal Text><Symbol>????:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
0592 <Normal Text> except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_BUSEE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
0593 <Normal Text> </Normal Text><Keyword>end</Keyword><br/>
0594 <Normal Text> </Normal Text><Binary>14'b00_0001_</Binary><Symbol>????</Symbol><Normal Text>_</Normal Text><Symbol>????:</Symbol><br/>
0595 <Normal Text> except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_IIE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
0596 <Normal Text> </Normal Text><Binary>14'b00_0000_1</Binary><Symbol>???</Symbol><Normal Text>_</Normal Text><Symbol>????:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
0597 <Normal Text> except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_AE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
0598 <Normal Text> </Normal Text><Keyword>end</Keyword><br/>
0599 <Normal Text> </Normal Text><Binary>14'b00_0000_01</Binary><Symbol>??</Symbol><Normal Text>_</Normal Text><Symbol>????:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
0600 <Normal Text> except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_DME</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
0601 <Normal Text> </Normal Text><Keyword>end</Keyword><br/>
0602 <Normal Text> </Normal Text><Binary>14'b00_0000_001</Binary><Symbol>?</Symbol><Normal Text>_</Normal Text><Symbol>????:</Symbol><br/>
0603 <Normal Text> except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_DPFE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
0604 <Normal Text> </Normal Text><Binary>14'b00_0000_0001_</Binary><Symbol>????:</Symbol><br/>
0605 <Normal Text> except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_BUSEE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
0606 <Normal Text> </Normal Text><Binary>14'b00_0000_0000_1</Binary><Symbol>???:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
0607 <Normal Text> except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_RE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
0608 <Normal Text> </Normal Text><Keyword>end</Keyword><br/>
0609 <Normal Text> </Normal Text><Binary>14'b00_0000_0000_01</Binary><Symbol>??:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
0610 <Normal Text> except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_TE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>~</Symbol><Normal Text>ex_freeze_q</Normal Text><Symbol>;</Symbol><br/>
0611 <Normal Text> </Normal Text><Keyword>end</Keyword><br/>
0612 <Normal Text> </Normal Text><Binary>14'b00_0000_0000_001</Binary><Symbol>?:</Symbol><Normal Text> </Normal Text><Keyword>begin</Keyword><br/>
0613 <Normal Text> except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_FPE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
0614 <Normal Text> </Normal Text><Keyword>end</Keyword><Normal Text> </Normal Text><br/>
0615 <Normal Text> </Normal Text><Binary>14'b00_0000_0000_0001</Binary><Symbol>:</Symbol><br/>
0616 <Normal Text> except_stop</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DRR_SCE</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>~</Symbol><Normal Text>ex_freeze_q</Normal Text><Symbol>;</Symbol><br/>
0617 <Normal Text> </Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><br/>
0618 <Normal Text> except_stop </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>14'b00_0000_0000_0000</Binary><Symbol>;</Symbol><br/>
0619 <Normal Text> </Normal Text><Keyword>endcase</Keyword><Normal Text> </Normal Text><Comment>// casez (du_except_stop)</Comment><br/>
0620 <Keyword>end</Keyword><br/>
0621 <Normal Text></Normal Text><br/>
0622 <Comment>//</Comment><br/>
0623 <Comment>// dbg_bp_o is registered</Comment><br/>
0624 <Comment>//</Comment><br/>
0625 <Keyword>assign</Keyword><Normal Text> dbg_bp_o </Normal Text><Symbol>=</Symbol><Normal Text> dbg_bp_r</Normal Text><Symbol>;</Symbol><br/>
0626 <Normal Text></Normal Text><br/>
0627 <Comment>//</Comment><br/>
0628 <Comment>// Breakpoint activation register</Comment><br/>
0629 <Comment>//</Comment><br/>
0630 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0631 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0632 <Normal Text> dbg_bp_r </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
0633 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(!</Symbol><Normal Text>ex_freeze</Normal Text><Symbol>)</Symbol><br/>
0634 <Normal Text> dbg_bp_r </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Symbol>|</Symbol><Normal Text>except_stop</Normal Text><br/>
0635 <Preprocessor>`ifdef OR1200_DU_DMR1_ST</Preprocessor><br/>
0636 <Normal Text> </Normal Text><Symbol>|</Symbol><Normal Text> </Normal Text><Symbol>~((</Symbol><Normal Text>ex_insn</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>26</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_OR32_NOP</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> ex_insn</Normal Text><Symbol>[</Symbol><Integer>16</Integer><Symbol>])</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_ST</Preprocessor><Symbol>]</Symbol><br/>
0637 <Preprocessor>`endif</Preprocessor><br/>
0638 <Preprocessor>`ifdef OR1200_DU_DMR1_BT</Preprocessor><br/>
0639 <Normal Text> </Normal Text><Symbol>|</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>branch_op </Normal Text><Symbol>!=</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_BRANCHOP_NOP</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>branch_op </Normal Text><Symbol>!=</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_BRANCHOP_RFE</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_BT</Preprocessor><Symbol>]</Symbol><br/>
0640 <Preprocessor>`endif</Preprocessor><br/>
0641 <Normal Text> </Normal Text><Symbol>;</Symbol><br/>
0642 <Normal Text> </Normal Text><Keyword>else</Keyword><br/>
0643 <Normal Text> dbg_bp_r </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Symbol>|</Symbol><Normal Text>except_stop</Normal Text><Symbol>;</Symbol><br/>
0644 <Normal Text></Normal Text><br/>
0645 <Comment>//</Comment><br/>
0646 <Comment>// Write to DMR1</Comment><br/>
0647 <Comment>//</Comment><br/>
0648 <Preprocessor>`ifdef OR1200_DU_DMR1</Preprocessor><br/>
0649 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0650 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0651 <Normal Text> dmr1 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>25'h000_0000</Hex><Symbol>;</Symbol><br/>
0652 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0653 <Preprocessor>`ifdef OR1200_DU_HWBKPTS</Preprocessor><br/>
0654 <Normal Text> dmr1 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>24</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0655 <Preprocessor>`else</Preprocessor><br/>
0656 <Normal Text> dmr1 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Binary>1'b0</Binary><Symbol>,</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>23</Integer><Symbol>:</Symbol><Integer>22</Integer><Symbol>],</Symbol><Normal Text> </Normal Text><Hex>22'h00_0000</Hex><Symbol>};</Symbol><br/>
0657 <Preprocessor>`endif</Preprocessor><br/>
0658 <Preprocessor>`else</Preprocessor><br/>
0659 <Keyword>assign</Keyword><Normal Text> dmr1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>25'h000_0000</Hex><Symbol>;</Symbol><br/>
0660 <Preprocessor>`endif</Preprocessor><br/>
0661 <Normal Text></Normal Text><br/>
0662 <Comment>//</Comment><br/>
0663 <Comment>// Write to DMR2</Comment><br/>
0664 <Comment>//</Comment><br/>
0665 <Preprocessor>`ifdef OR1200_DU_DMR2</Preprocessor><br/>
0666 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0667 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0668 <Normal Text> dmr2 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>24'h00_0000</Hex><Symbol>;</Symbol><br/>
0669 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr2_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0670 <Normal Text> dmr2 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>23</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0671 <Preprocessor>`else</Preprocessor><br/>
0672 <Keyword>assign</Keyword><Normal Text> dmr2 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>24'h00_0000</Hex><Symbol>;</Symbol><br/>
0673 <Preprocessor>`endif</Preprocessor><br/>
0674 <Normal Text></Normal Text><br/>
0675 <Comment>//</Comment><br/>
0676 <Comment>// Write to DSR</Comment><br/>
0677 <Comment>//</Comment><br/>
0678 <Preprocessor>`ifdef OR1200_DU_DSR</Preprocessor><br/>
0679 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0680 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0681 <Normal Text> dsr </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Preprocessor>`OR1200_DU_DSR_WIDTH</Preprocessor><Symbol>{</Symbol><Binary>1'b0</Binary><Symbol>}};</Symbol><br/>
0682 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dsr_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0683 <Normal Text> dsr </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DSR_WIDTH</Preprocessor><Symbol>-</Symbol><Integer>1</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0684 <Preprocessor>`else</Preprocessor><br/>
0685 <Keyword>assign</Keyword><Normal Text> dsr </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Preprocessor>`OR1200_DU_DSR_WIDTH</Preprocessor><Symbol>{</Symbol><Binary>1'b0</Binary><Symbol>}};</Symbol><br/>
0686 <Preprocessor>`endif</Preprocessor><br/>
0687 <Normal Text></Normal Text><br/>
0688 <Comment>//</Comment><br/>
0689 <Comment>// Write to DRR</Comment><br/>
0690 <Comment>//</Comment><br/>
0691 <Preprocessor>`ifdef OR1200_DU_DRR</Preprocessor><br/>
0692 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0693 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0694 <Normal Text> drr </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>14'b0</Binary><Symbol>;</Symbol><br/>
0695 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>drr_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0696 <Normal Text> drr </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>13</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0697 <Normal Text> </Normal Text><Keyword>else</Keyword><br/>
0698 <Normal Text> drr </Normal Text><Symbol><=</Symbol><Normal Text> drr </Normal Text><Symbol>|</Symbol><Normal Text> except_stop</Normal Text><Symbol>;</Symbol><br/>
0699 <Preprocessor>`else</Preprocessor><br/>
0700 <Keyword>assign</Keyword><Normal Text> drr </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>14'b0</Binary><Symbol>;</Symbol><br/>
0701 <Preprocessor>`endif</Preprocessor><br/>
0702 <Normal Text></Normal Text><br/>
0703 <Comment>//</Comment><br/>
0704 <Comment>// Write to DVR0</Comment><br/>
0705 <Comment>//</Comment><br/>
0706 <Preprocessor>`ifdef OR1200_DU_DVR0</Preprocessor><br/>
0707 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0708 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0709 <Normal Text> dvr0 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0710 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dvr0_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0711 <Normal Text> dvr0 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0712 <Preprocessor>`else</Preprocessor><br/>
0713 <Keyword>assign</Keyword><Normal Text> dvr0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0714 <Preprocessor>`endif</Preprocessor><br/>
0715 <Normal Text></Normal Text><br/>
0716 <Comment>//</Comment><br/>
0717 <Comment>// Write to DVR1</Comment><br/>
0718 <Comment>//</Comment><br/>
0719 <Preprocessor>`ifdef OR1200_DU_DVR1</Preprocessor><br/>
0720 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0721 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0722 <Normal Text> dvr1 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0723 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dvr1_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0724 <Normal Text> dvr1 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0725 <Preprocessor>`else</Preprocessor><br/>
0726 <Keyword>assign</Keyword><Normal Text> dvr1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0727 <Preprocessor>`endif</Preprocessor><br/>
0728 <Normal Text></Normal Text><br/>
0729 <Comment>//</Comment><br/>
0730 <Comment>// Write to DVR2</Comment><br/>
0731 <Comment>//</Comment><br/>
0732 <Preprocessor>`ifdef OR1200_DU_DVR2</Preprocessor><br/>
0733 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0734 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0735 <Normal Text> dvr2 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0736 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dvr2_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0737 <Normal Text> dvr2 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0738 <Preprocessor>`else</Preprocessor><br/>
0739 <Keyword>assign</Keyword><Normal Text> dvr2 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0740 <Preprocessor>`endif</Preprocessor><br/>
0741 <Normal Text></Normal Text><br/>
0742 <Comment>//</Comment><br/>
0743 <Comment>// Write to DVR3</Comment><br/>
0744 <Comment>//</Comment><br/>
0745 <Preprocessor>`ifdef OR1200_DU_DVR3</Preprocessor><br/>
0746 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0747 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0748 <Normal Text> dvr3 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0749 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dvr3_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0750 <Normal Text> dvr3 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0751 <Preprocessor>`else</Preprocessor><br/>
0752 <Keyword>assign</Keyword><Normal Text> dvr3 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0753 <Preprocessor>`endif</Preprocessor><br/>
0754 <Normal Text></Normal Text><br/>
0755 <Comment>//</Comment><br/>
0756 <Comment>// Write to DVR4</Comment><br/>
0757 <Comment>//</Comment><br/>
0758 <Preprocessor>`ifdef OR1200_DU_DVR4</Preprocessor><br/>
0759 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0760 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0761 <Normal Text> dvr4 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0762 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dvr4_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0763 <Normal Text> dvr4 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0764 <Preprocessor>`else</Preprocessor><br/>
0765 <Keyword>assign</Keyword><Normal Text> dvr4 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0766 <Preprocessor>`endif</Preprocessor><br/>
0767 <Normal Text></Normal Text><br/>
0768 <Comment>//</Comment><br/>
0769 <Comment>// Write to DVR5</Comment><br/>
0770 <Comment>//</Comment><br/>
0771 <Preprocessor>`ifdef OR1200_DU_DVR5</Preprocessor><br/>
0772 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0773 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0774 <Normal Text> dvr5 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0775 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dvr5_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0776 <Normal Text> dvr5 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0777 <Preprocessor>`else</Preprocessor><br/>
0778 <Keyword>assign</Keyword><Normal Text> dvr5 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0779 <Preprocessor>`endif</Preprocessor><br/>
0780 <Normal Text></Normal Text><br/>
0781 <Comment>//</Comment><br/>
0782 <Comment>// Write to DVR6</Comment><br/>
0783 <Comment>//</Comment><br/>
0784 <Preprocessor>`ifdef OR1200_DU_DVR6</Preprocessor><br/>
0785 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0786 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0787 <Normal Text> dvr6 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0788 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dvr6_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0789 <Normal Text> dvr6 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0790 <Preprocessor>`else</Preprocessor><br/>
0791 <Keyword>assign</Keyword><Normal Text> dvr6 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0792 <Preprocessor>`endif</Preprocessor><br/>
0793 <Normal Text></Normal Text><br/>
0794 <Comment>//</Comment><br/>
0795 <Comment>// Write to DVR7</Comment><br/>
0796 <Comment>//</Comment><br/>
0797 <Preprocessor>`ifdef OR1200_DU_DVR7</Preprocessor><br/>
0798 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0799 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0800 <Normal Text> dvr7 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0801 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dvr7_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0802 <Normal Text> dvr7 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0803 <Preprocessor>`else</Preprocessor><br/>
0804 <Keyword>assign</Keyword><Normal Text> dvr7 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0805 <Preprocessor>`endif</Preprocessor><br/>
0806 <Normal Text></Normal Text><br/>
0807 <Comment>//</Comment><br/>
0808 <Comment>// Write to DCR0</Comment><br/>
0809 <Comment>//</Comment><br/>
0810 <Preprocessor>`ifdef OR1200_DU_DCR0</Preprocessor><br/>
0811 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0812 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0813 <Normal Text> dcr0 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
0814 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr0_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0815 <Normal Text> dcr0 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0816 <Preprocessor>`else</Preprocessor><br/>
0817 <Keyword>assign</Keyword><Normal Text> dcr0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
0818 <Preprocessor>`endif</Preprocessor><br/>
0819 <Normal Text></Normal Text><br/>
0820 <Comment>//</Comment><br/>
0821 <Comment>// Write to DCR1</Comment><br/>
0822 <Comment>//</Comment><br/>
0823 <Preprocessor>`ifdef OR1200_DU_DCR1</Preprocessor><br/>
0824 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0825 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0826 <Normal Text> dcr1 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
0827 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr1_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0828 <Normal Text> dcr1 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0829 <Preprocessor>`else</Preprocessor><br/>
0830 <Keyword>assign</Keyword><Normal Text> dcr1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
0831 <Preprocessor>`endif</Preprocessor><br/>
0832 <Normal Text></Normal Text><br/>
0833 <Comment>//</Comment><br/>
0834 <Comment>// Write to DCR2</Comment><br/>
0835 <Comment>//</Comment><br/>
0836 <Preprocessor>`ifdef OR1200_DU_DCR2</Preprocessor><br/>
0837 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0838 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0839 <Normal Text> dcr2 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
0840 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr2_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0841 <Normal Text> dcr2 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0842 <Preprocessor>`else</Preprocessor><br/>
0843 <Keyword>assign</Keyword><Normal Text> dcr2 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
0844 <Preprocessor>`endif</Preprocessor><br/>
0845 <Normal Text></Normal Text><br/>
0846 <Comment>//</Comment><br/>
0847 <Comment>// Write to DCR3</Comment><br/>
0848 <Comment>//</Comment><br/>
0849 <Preprocessor>`ifdef OR1200_DU_DCR3</Preprocessor><br/>
0850 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0851 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0852 <Normal Text> dcr3 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
0853 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr3_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0854 <Normal Text> dcr3 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0855 <Preprocessor>`else</Preprocessor><br/>
0856 <Keyword>assign</Keyword><Normal Text> dcr3 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
0857 <Preprocessor>`endif</Preprocessor><br/>
0858 <Normal Text></Normal Text><br/>
0859 <Comment>//</Comment><br/>
0860 <Comment>// Write to DCR4</Comment><br/>
0861 <Comment>//</Comment><br/>
0862 <Preprocessor>`ifdef OR1200_DU_DCR4</Preprocessor><br/>
0863 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0864 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0865 <Normal Text> dcr4 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
0866 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr4_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0867 <Normal Text> dcr4 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0868 <Preprocessor>`else</Preprocessor><br/>
0869 <Keyword>assign</Keyword><Normal Text> dcr4 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
0870 <Preprocessor>`endif</Preprocessor><br/>
0871 <Normal Text></Normal Text><br/>
0872 <Comment>//</Comment><br/>
0873 <Comment>// Write to DCR5</Comment><br/>
0874 <Comment>//</Comment><br/>
0875 <Preprocessor>`ifdef OR1200_DU_DCR5</Preprocessor><br/>
0876 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0877 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0878 <Normal Text> dcr5 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
0879 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr5_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0880 <Normal Text> dcr5 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0881 <Preprocessor>`else</Preprocessor><br/>
0882 <Keyword>assign</Keyword><Normal Text> dcr5 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
0883 <Preprocessor>`endif</Preprocessor><br/>
0884 <Normal Text></Normal Text><br/>
0885 <Comment>//</Comment><br/>
0886 <Comment>// Write to DCR6</Comment><br/>
0887 <Comment>//</Comment><br/>
0888 <Preprocessor>`ifdef OR1200_DU_DCR6</Preprocessor><br/>
0889 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0890 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0891 <Normal Text> dcr6 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
0892 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr6_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0893 <Normal Text> dcr6 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0894 <Preprocessor>`else</Preprocessor><br/>
0895 <Keyword>assign</Keyword><Normal Text> dcr6 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
0896 <Preprocessor>`endif</Preprocessor><br/>
0897 <Normal Text></Normal Text><br/>
0898 <Comment>//</Comment><br/>
0899 <Comment>// Write to DCR7</Comment><br/>
0900 <Comment>//</Comment><br/>
0901 <Preprocessor>`ifdef OR1200_DU_DCR7</Preprocessor><br/>
0902 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0903 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0904 <Normal Text> dcr7 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
0905 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr7_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0906 <Normal Text> dcr7 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0907 <Preprocessor>`else</Preprocessor><br/>
0908 <Keyword>assign</Keyword><Normal Text> dcr7 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
0909 <Preprocessor>`endif</Preprocessor><br/>
0910 <Normal Text></Normal Text><br/>
0911 <Comment>//</Comment><br/>
0912 <Comment>// Write to DWCR0</Comment><br/>
0913 <Comment>//</Comment><br/>
0914 <Preprocessor>`ifdef OR1200_DU_DWCR0</Preprocessor><br/>
0915 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0916 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0917 <Normal Text> dwcr0 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0918 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dwcr0_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0919 <Normal Text> dwcr0 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0920 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>incr_wpcntr0</Normal Text><Symbol>)</Symbol><br/>
0921 <Normal Text> dwcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DWCR_COUNT</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><Normal Text> dwcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DWCR_COUNT</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>+</Symbol><Normal Text> </Normal Text><Hex>16'h0001</Hex><Symbol>;</Symbol><br/>
0922 <Preprocessor>`else</Preprocessor><br/>
0923 <Keyword>assign</Keyword><Normal Text> dwcr0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0924 <Preprocessor>`endif</Preprocessor><br/>
0925 <Normal Text></Normal Text><br/>
0926 <Comment>//</Comment><br/>
0927 <Comment>// Write to DWCR1</Comment><br/>
0928 <Comment>//</Comment><br/>
0929 <Preprocessor>`ifdef OR1200_DU_DWCR1</Preprocessor><br/>
0930 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
0931 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
0932 <Normal Text> dwcr1 </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0933 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dwcr1_sel </Normal Text><Symbol>&&</Symbol><Normal Text> spr_write</Normal Text><Symbol>)</Symbol><br/>
0934 <Normal Text> dwcr1 </Normal Text><Symbol><=</Symbol><Normal Text> spr_dat_i</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
0935 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>incr_wpcntr1</Normal Text><Symbol>)</Symbol><br/>
0936 <Normal Text> dwcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DWCR_COUNT</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><Normal Text> dwcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DWCR_COUNT</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>+</Symbol><Normal Text> </Normal Text><Hex>16'h0001</Hex><Symbol>;</Symbol><br/>
0937 <Preprocessor>`else</Preprocessor><br/>
0938 <Keyword>assign</Keyword><Normal Text> dwcr1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
0939 <Preprocessor>`endif</Preprocessor><br/>
0940 <Normal Text></Normal Text><br/>
0941 <Comment>//</Comment><br/>
0942 <Comment>// Read DU registers</Comment><br/>
0943 <Comment>//</Comment><br/>
0944 <Preprocessor>`ifdef OR1200_DU_READREGS</Preprocessor><br/>
0945 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>spr_addr </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dsr </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> drr </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dmr2</Normal Text><br/>
0946 <Normal Text> </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr0 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr2 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr3 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr4</Normal Text><br/>
0947 <Normal Text> </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr5 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr6 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr7</Normal Text><br/>
0948 <Normal Text> </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr0 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr2 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr3 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr4</Normal Text><br/>
0949 <Normal Text> </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr5 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr6 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr7</Normal Text><br/>
0950 <Normal Text> </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dwcr0 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dwcr1</Normal Text><br/>
0951 <Preprocessor>`ifdef OR1200_DU_TB_IMPLEMENTED</Preprocessor><br/>
0952 <Normal Text> </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> tb_wadr </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> tbia_dat_o </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> tbim_dat_o</Normal Text><br/>
0953 <Normal Text> </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> tbar_dat_o </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> tbts_dat_o</Normal Text><br/>
0954 <Preprocessor>`endif</Preprocessor><br/>
0955 <Normal Text> </Normal Text><Symbol>)</Symbol><br/>
0956 <Normal Text> </Normal Text><Keyword>casez</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DUOFS_BITS</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Comment>// synopsys parallel_case</Comment><br/>
0957 <Preprocessor>`ifdef OR1200_DU_DVR0</Preprocessor><br/>
0958 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR0</Preprocessor><Symbol>:</Symbol><br/>
0959 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dvr0</Normal Text><Symbol>;</Symbol><br/>
0960 <Preprocessor>`endif</Preprocessor><br/>
0961 <Preprocessor>`ifdef OR1200_DU_DVR1</Preprocessor><br/>
0962 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR1</Preprocessor><Symbol>:</Symbol><br/>
0963 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dvr1</Normal Text><Symbol>;</Symbol><br/>
0964 <Preprocessor>`endif</Preprocessor><br/>
0965 <Preprocessor>`ifdef OR1200_DU_DVR2</Preprocessor><br/>
0966 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR2</Preprocessor><Symbol>:</Symbol><br/>
0967 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dvr2</Normal Text><Symbol>;</Symbol><br/>
0968 <Preprocessor>`endif</Preprocessor><br/>
0969 <Preprocessor>`ifdef OR1200_DU_DVR3</Preprocessor><br/>
0970 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR3</Preprocessor><Symbol>:</Symbol><br/>
0971 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dvr3</Normal Text><Symbol>;</Symbol><br/>
0972 <Preprocessor>`endif</Preprocessor><br/>
0973 <Preprocessor>`ifdef OR1200_DU_DVR4</Preprocessor><br/>
0974 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR4</Preprocessor><Symbol>:</Symbol><br/>
0975 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dvr4</Normal Text><Symbol>;</Symbol><br/>
0976 <Preprocessor>`endif</Preprocessor><br/>
0977 <Preprocessor>`ifdef OR1200_DU_DVR5</Preprocessor><br/>
0978 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR5</Preprocessor><Symbol>:</Symbol><br/>
0979 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dvr5</Normal Text><Symbol>;</Symbol><br/>
0980 <Preprocessor>`endif</Preprocessor><br/>
0981 <Preprocessor>`ifdef OR1200_DU_DVR6</Preprocessor><br/>
0982 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR6</Preprocessor><Symbol>:</Symbol><br/>
0983 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dvr6</Normal Text><Symbol>;</Symbol><br/>
0984 <Preprocessor>`endif</Preprocessor><br/>
0985 <Preprocessor>`ifdef OR1200_DU_DVR7</Preprocessor><br/>
0986 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DVR7</Preprocessor><Symbol>:</Symbol><br/>
0987 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dvr7</Normal Text><Symbol>;</Symbol><br/>
0988 <Preprocessor>`endif</Preprocessor><br/>
0989 <Preprocessor>`ifdef OR1200_DU_DCR0</Preprocessor><br/>
0990 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR0</Preprocessor><Symbol>:</Symbol><br/>
0991 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>24'h00_0000</Hex><Symbol>,</Symbol><Normal Text> dcr0</Normal Text><Symbol>};</Symbol><br/>
0992 <Preprocessor>`endif</Preprocessor><br/>
0993 <Preprocessor>`ifdef OR1200_DU_DCR1</Preprocessor><br/>
0994 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR1</Preprocessor><Symbol>:</Symbol><br/>
0995 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>24'h00_0000</Hex><Symbol>,</Symbol><Normal Text> dcr1</Normal Text><Symbol>};</Symbol><br/>
0996 <Preprocessor>`endif</Preprocessor><br/>
0997 <Preprocessor>`ifdef OR1200_DU_DCR2</Preprocessor><br/>
0998 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR2</Preprocessor><Symbol>:</Symbol><br/>
0999 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>24'h00_0000</Hex><Symbol>,</Symbol><Normal Text> dcr2</Normal Text><Symbol>};</Symbol><br/>
1000 <Preprocessor>`endif</Preprocessor><br/>
1001 <Preprocessor>`ifdef OR1200_DU_DCR3</Preprocessor><br/>
1002 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR3</Preprocessor><Symbol>:</Symbol><br/>
1003 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>24'h00_0000</Hex><Symbol>,</Symbol><Normal Text> dcr3</Normal Text><Symbol>};</Symbol><br/>
1004 <Preprocessor>`endif</Preprocessor><br/>
1005 <Preprocessor>`ifdef OR1200_DU_DCR4</Preprocessor><br/>
1006 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR4</Preprocessor><Symbol>:</Symbol><br/>
1007 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>24'h00_0000</Hex><Symbol>,</Symbol><Normal Text> dcr4</Normal Text><Symbol>};</Symbol><br/>
1008 <Preprocessor>`endif</Preprocessor><br/>
1009 <Preprocessor>`ifdef OR1200_DU_DCR5</Preprocessor><br/>
1010 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR5</Preprocessor><Symbol>:</Symbol><br/>
1011 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>24'h00_0000</Hex><Symbol>,</Symbol><Normal Text> dcr5</Normal Text><Symbol>};</Symbol><br/>
1012 <Preprocessor>`endif</Preprocessor><br/>
1013 <Preprocessor>`ifdef OR1200_DU_DCR6</Preprocessor><br/>
1014 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR6</Preprocessor><Symbol>:</Symbol><br/>
1015 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>24'h00_0000</Hex><Symbol>,</Symbol><Normal Text> dcr6</Normal Text><Symbol>};</Symbol><br/>
1016 <Preprocessor>`endif</Preprocessor><br/>
1017 <Preprocessor>`ifdef OR1200_DU_DCR7</Preprocessor><br/>
1018 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DCR7</Preprocessor><Symbol>:</Symbol><br/>
1019 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>24'h00_0000</Hex><Symbol>,</Symbol><Normal Text> dcr7</Normal Text><Symbol>};</Symbol><br/>
1020 <Preprocessor>`endif</Preprocessor><br/>
1021 <Preprocessor>`ifdef OR1200_DU_DMR1</Preprocessor><br/>
1022 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DMR1</Preprocessor><Symbol>:</Symbol><br/>
1023 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>7'h00</Hex><Symbol>,</Symbol><Normal Text> dmr1</Normal Text><Symbol>};</Symbol><br/>
1024 <Preprocessor>`endif</Preprocessor><br/>
1025 <Preprocessor>`ifdef OR1200_DU_DMR2</Preprocessor><br/>
1026 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DMR2</Preprocessor><Symbol>:</Symbol><br/>
1027 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>8'h00</Hex><Symbol>,</Symbol><Normal Text> dmr2</Normal Text><Symbol>};</Symbol><br/>
1028 <Preprocessor>`endif</Preprocessor><br/>
1029 <Preprocessor>`ifdef OR1200_DU_DWCR0</Preprocessor><br/>
1030 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DWCR0</Preprocessor><Symbol>:</Symbol><br/>
1031 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dwcr0</Normal Text><Symbol>;</Symbol><br/>
1032 <Preprocessor>`endif</Preprocessor><br/>
1033 <Preprocessor>`ifdef OR1200_DU_DWCR1</Preprocessor><br/>
1034 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DWCR1</Preprocessor><Symbol>:</Symbol><br/>
1035 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> dwcr1</Normal Text><Symbol>;</Symbol><br/>
1036 <Preprocessor>`endif</Preprocessor><br/>
1037 <Preprocessor>`ifdef OR1200_DU_DSR</Preprocessor><br/>
1038 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DSR</Preprocessor><Symbol>:</Symbol><br/>
1039 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Binary>18'b0</Binary><Symbol>,</Symbol><Normal Text> dsr</Normal Text><Symbol>};</Symbol><br/>
1040 <Preprocessor>`endif</Preprocessor><br/>
1041 <Preprocessor>`ifdef OR1200_DU_DRR</Preprocessor><br/>
1042 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_DRR</Preprocessor><Symbol>:</Symbol><br/>
1043 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Binary>18'b0</Binary><Symbol>,</Symbol><Normal Text> drr</Normal Text><Symbol>};</Symbol><br/>
1044 <Preprocessor>`endif</Preprocessor><br/>
1045 <Preprocessor>`ifdef OR1200_DU_TB_IMPLEMENTED</Preprocessor><br/>
1046 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_TBADR</Preprocessor><Symbol>:</Symbol><br/>
1047 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Hex>24'h000000</Hex><Symbol>,</Symbol><Normal Text> tb_wadr</Normal Text><Symbol>};</Symbol><br/>
1048 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_TBIA</Preprocessor><Symbol>:</Symbol><br/>
1049 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> tbia_dat_o</Normal Text><Symbol>;</Symbol><br/>
1050 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_TBIM</Preprocessor><Symbol>:</Symbol><br/>
1051 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> tbim_dat_o</Normal Text><Symbol>;</Symbol><br/>
1052 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_TBAR</Preprocessor><Symbol>:</Symbol><br/>
1053 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> tbar_dat_o</Normal Text><Symbol>;</Symbol><br/>
1054 <Normal Text> </Normal Text><Preprocessor>`OR1200_DU_TBTS</Preprocessor><Symbol>:</Symbol><br/>
1055 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> tbts_dat_o</Normal Text><Symbol>;</Symbol><br/>
1056 <Preprocessor>`endif</Preprocessor><br/>
1057 <Normal Text> </Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><br/>
1058 <Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
1059 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1060 <Preprocessor>`endif</Preprocessor><br/>
1061 <Normal Text></Normal Text><br/>
1062 <Comment>//</Comment><br/>
1063 <Comment>// DSR alias</Comment><br/>
1064 <Comment>//</Comment><br/>
1065 <Keyword>assign</Keyword><Normal Text> du_dsr </Normal Text><Symbol>=</Symbol><Normal Text> dsr</Normal Text><Symbol>;</Symbol><br/>
1066 <Normal Text></Normal Text><br/>
1067 <Preprocessor>`ifdef OR1200_DU_HWBKPTS</Preprocessor><br/>
1068 <Normal Text></Normal Text><br/>
1069 <Comment>//</Comment><br/>
1070 <Comment>// Compare To What (Match Condition 0)</Comment><br/>
1071 <Comment>//</Comment><br/>
1072 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr0 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> id_pc </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_adr_i </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_dc</Normal Text><br/>
1073 <Normal Text> </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_lsu </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_we_i</Normal Text><Symbol>)</Symbol><br/>
1074 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Comment>// synopsys parallel_case</Comment><br/>
1075 <Normal Text> </Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text> match_cond0_ct </Normal Text><Symbol>=</Symbol><Normal Text> id_pc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// insn fetch EA</Comment><br/>
1076 <Normal Text> </Normal Text><Binary>3'b010</Binary><Symbol>:</Symbol><Normal Text> match_cond0_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load EA</Comment><br/>
1077 <Normal Text> </Normal Text><Binary>3'b011</Binary><Symbol>:</Symbol><Normal Text> match_cond0_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// store EA</Comment><br/>
1078 <Normal Text> </Normal Text><Binary>3'b100</Binary><Symbol>:</Symbol><Normal Text> match_cond0_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load data</Comment><br/>
1079 <Normal Text> </Normal Text><Binary>3'b101</Binary><Symbol>:</Symbol><Normal Text> match_cond0_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// store data</Comment><br/>
1080 <Normal Text> </Normal Text><Binary>3'b110</Binary><Symbol>:</Symbol><Normal Text> match_cond0_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load/store EA</Comment><br/>
1081 <Normal Text> </Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond0_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_we_i </Normal Text><Symbol>?</Symbol><Normal Text> dcpu_dat_lsu </Normal Text><Symbol>:</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><br/>
1082 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1083 <Normal Text></Normal Text><br/>
1084 <Comment>//</Comment><br/>
1085 <Comment>// When To Compare (Match Condition 0)</Comment><br/>
1086 <Comment>//</Comment><br/>
1087 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr0 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>)</Symbol><br/>
1088 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Comment>// synopsys parallel_case</Comment><br/>
1089 <Normal Text> </Normal Text><Binary>3'b000</Binary><Symbol>:</Symbol><Normal Text> match_cond0_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>//comparison disabled</Comment><br/>
1090 <Normal Text> </Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text> match_cond0_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// insn fetch EA</Comment><br/>
1091 <Normal Text> </Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond0_stb </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// any load/store</Comment><br/>
1092 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1093 <Normal Text></Normal Text><br/>
1094 <Comment>//</Comment><br/>
1095 <Comment>// Match Condition 0</Comment><br/>
1096 <Comment>//</Comment><br/>
1097 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>match_cond0_stb </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr0 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr0 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match_cond0_ct</Normal Text><Symbol>)</Symbol><br/>
1098 <Normal Text> </Normal Text><Keyword>casex</Keyword><Normal Text> </Normal Text><Symbol>({</Symbol><Normal Text>match_cond0_stb</Normal Text><Symbol>,</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CC</Preprocessor><Symbol>]})</Symbol><br/>
1099 <Normal Text> </Normal Text><Binary>4'b0_xxx</Binary><Symbol>,</Symbol><br/>
1100 <Normal Text> </Normal Text><Binary>4'b1_000</Binary><Symbol>,</Symbol><br/>
1101 <Normal Text> </Normal Text><Binary>4'b1_111</Binary><Symbol>:</Symbol><Normal Text> match0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1102 <Normal Text> </Normal Text><Binary>4'b1_001</Binary><Symbol>:</Symbol><Normal Text> match0 </Normal Text><Symbol>=</Symbol><br/>
1103 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><br/>
1104 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr0</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr0</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1105 <Normal Text> </Normal Text><Binary>4'b1_010</Binary><Symbol>:</Symbol><Normal Text> match0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1106 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><</Symbol><br/>
1107 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr0</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr0</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1108 <Normal Text> </Normal Text><Binary>4'b1_011</Binary><Symbol>:</Symbol><Normal Text> match0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1109 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><br/>
1110 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr0</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr0</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1111 <Normal Text> </Normal Text><Binary>4'b1_100</Binary><Symbol>:</Symbol><Normal Text> match0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1112 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>></Symbol><br/>
1113 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr0</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr0</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1114 <Normal Text> </Normal Text><Binary>4'b1_101</Binary><Symbol>:</Symbol><Normal Text> match0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1115 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>>=</Symbol><br/>
1116 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr0</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr0</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1117 <Normal Text> </Normal Text><Binary>4'b1_110</Binary><Symbol>:</Symbol><Normal Text> match0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1118 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond0_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>!=</Symbol><br/>
1119 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr0</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr0</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1120 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1121 <Normal Text></Normal Text><br/>
1122 <Comment>//</Comment><br/>
1123 <Comment>// Watchpoint 0</Comment><br/>
1124 <Comment>//</Comment><br/>
1125 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match0</Normal Text><Symbol>)</Symbol><br/>
1126 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW0</Preprocessor><Symbol>])</Symbol><br/>
1127 <Normal Text> </Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match0</Normal Text><Symbol>;</Symbol><br/>
1128 <Normal Text> </Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match0</Normal Text><Symbol>;</Symbol><br/>
1129 <Normal Text> </Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match0</Normal Text><Symbol>;</Symbol><br/>
1130 <Normal Text> </Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>0</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1131 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1132 <Normal Text></Normal Text><br/>
1133 <Comment>//</Comment><br/>
1134 <Comment>// Compare To What (Match Condition 1)</Comment><br/>
1135 <Comment>//</Comment><br/>
1136 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> id_pc </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_adr_i </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_dc</Normal Text><br/>
1137 <Normal Text> </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_lsu </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_we_i</Normal Text><Symbol>)</Symbol><br/>
1138 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Comment>// synopsys parallel_case</Comment><br/>
1139 <Normal Text> </Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text> match_cond1_ct </Normal Text><Symbol>=</Symbol><Normal Text> id_pc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// insn fetch EA</Comment><br/>
1140 <Normal Text> </Normal Text><Binary>3'b010</Binary><Symbol>:</Symbol><Normal Text> match_cond1_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load EA</Comment><br/>
1141 <Normal Text> </Normal Text><Binary>3'b011</Binary><Symbol>:</Symbol><Normal Text> match_cond1_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// store EA</Comment><br/>
1142 <Normal Text> </Normal Text><Binary>3'b100</Binary><Symbol>:</Symbol><Normal Text> match_cond1_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load data</Comment><br/>
1143 <Normal Text> </Normal Text><Binary>3'b101</Binary><Symbol>:</Symbol><Normal Text> match_cond1_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// store data</Comment><br/>
1144 <Normal Text> </Normal Text><Binary>3'b110</Binary><Symbol>:</Symbol><Normal Text> match_cond1_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load/store EA</Comment><br/>
1145 <Normal Text> </Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond1_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_we_i </Normal Text><Symbol>?</Symbol><Normal Text> dcpu_dat_lsu </Normal Text><Symbol>:</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><br/>
1146 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1147 <Normal Text></Normal Text><br/>
1148 <Comment>//</Comment><br/>
1149 <Comment>// When To Compare (Match Condition 1)</Comment><br/>
1150 <Comment>//</Comment><br/>
1151 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>)</Symbol><br/>
1152 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Comment>// synopsys parallel_case</Comment><br/>
1153 <Normal Text> </Normal Text><Binary>3'b000</Binary><Symbol>:</Symbol><Normal Text> match_cond1_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>//comparison disabled</Comment><br/>
1154 <Normal Text> </Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text> match_cond1_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// insn fetch EA</Comment><br/>
1155 <Normal Text> </Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond1_stb </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// any load/store</Comment><br/>
1156 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1157 <Normal Text></Normal Text><br/>
1158 <Comment>//</Comment><br/>
1159 <Comment>// Match Condition 1</Comment><br/>
1160 <Comment>//</Comment><br/>
1161 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>match_cond1_stb </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match_cond1_ct</Normal Text><Symbol>)</Symbol><br/>
1162 <Normal Text> </Normal Text><Keyword>casex</Keyword><Normal Text> </Normal Text><Symbol>({</Symbol><Normal Text>match_cond1_stb</Normal Text><Symbol>,</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CC</Preprocessor><Symbol>]})</Symbol><br/>
1163 <Normal Text> </Normal Text><Binary>4'b0_xxx</Binary><Symbol>,</Symbol><br/>
1164 <Normal Text> </Normal Text><Binary>4'b1_000</Binary><Symbol>,</Symbol><br/>
1165 <Normal Text> </Normal Text><Binary>4'b1_111</Binary><Symbol>:</Symbol><Normal Text> match1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1166 <Normal Text> </Normal Text><Binary>4'b1_001</Binary><Symbol>:</Symbol><Normal Text> match1 </Normal Text><Symbol>=</Symbol><br/>
1167 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><br/>
1168 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr1</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr1</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1169 <Normal Text> </Normal Text><Binary>4'b1_010</Binary><Symbol>:</Symbol><Normal Text> match1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1170 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><</Symbol><br/>
1171 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr1</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr1</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1172 <Normal Text> </Normal Text><Binary>4'b1_011</Binary><Symbol>:</Symbol><Normal Text> match1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1173 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><br/>
1174 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr1</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr1</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1175 <Normal Text> </Normal Text><Binary>4'b1_100</Binary><Symbol>:</Symbol><Normal Text> match1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1176 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>></Symbol><br/>
1177 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr1</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr1</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1178 <Normal Text> </Normal Text><Binary>4'b1_101</Binary><Symbol>:</Symbol><Normal Text> match1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1179 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>>=</Symbol><br/>
1180 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr1</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr1</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1181 <Normal Text> </Normal Text><Binary>4'b1_110</Binary><Symbol>:</Symbol><Normal Text> match1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1182 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond1_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>!=</Symbol><br/>
1183 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr1</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr1</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1184 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1185 <Normal Text></Normal Text><br/>
1186 <Comment>//</Comment><br/>
1187 <Comment>// Watchpoint 1</Comment><br/>
1188 <Comment>//</Comment><br/>
1189 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
1190 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW1</Preprocessor><Symbol>])</Symbol><br/>
1191 <Normal Text> </Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>1</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match1</Normal Text><Symbol>;</Symbol><br/>
1192 <Normal Text> </Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>1</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match1 </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
1193 <Normal Text> </Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>1</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match1 </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>0</Integer><Symbol>];</Symbol><br/>
1194 <Normal Text> </Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>1</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1195 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1196 <Normal Text></Normal Text><br/>
1197 <Comment>//</Comment><br/>
1198 <Comment>// Compare To What (Match Condition 2)</Comment><br/>
1199 <Comment>//</Comment><br/>
1200 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr2 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> id_pc </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_adr_i </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_dc</Normal Text><br/>
1201 <Normal Text> </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_lsu </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_we_i</Normal Text><Symbol>)</Symbol><br/>
1202 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Comment>// synopsys parallel_case</Comment><br/>
1203 <Normal Text> </Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text> match_cond2_ct </Normal Text><Symbol>=</Symbol><Normal Text> id_pc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// insn fetch EA</Comment><br/>
1204 <Normal Text> </Normal Text><Binary>3'b010</Binary><Symbol>:</Symbol><Normal Text> match_cond2_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load EA</Comment><br/>
1205 <Normal Text> </Normal Text><Binary>3'b011</Binary><Symbol>:</Symbol><Normal Text> match_cond2_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// store EA</Comment><br/>
1206 <Normal Text> </Normal Text><Binary>3'b100</Binary><Symbol>:</Symbol><Normal Text> match_cond2_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load data</Comment><br/>
1207 <Normal Text> </Normal Text><Binary>3'b101</Binary><Symbol>:</Symbol><Normal Text> match_cond2_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// store data</Comment><br/>
1208 <Normal Text> </Normal Text><Binary>3'b110</Binary><Symbol>:</Symbol><Normal Text> match_cond2_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load/store EA</Comment><br/>
1209 <Normal Text> </Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond2_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_we_i </Normal Text><Symbol>?</Symbol><Normal Text> dcpu_dat_lsu </Normal Text><Symbol>:</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><br/>
1210 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1211 <Normal Text></Normal Text><br/>
1212 <Comment>//</Comment><br/>
1213 <Comment>// When To Compare (Match Condition 2)</Comment><br/>
1214 <Comment>//</Comment><br/>
1215 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr2 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>)</Symbol><br/>
1216 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Comment>// synopsys parallel_case</Comment><br/>
1217 <Normal Text> </Normal Text><Binary>3'b000</Binary><Symbol>:</Symbol><Normal Text> match_cond2_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>//comparison disabled</Comment><br/>
1218 <Normal Text> </Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text> match_cond2_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// insn fetch EA</Comment><br/>
1219 <Normal Text> </Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond2_stb </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// any load/store</Comment><br/>
1220 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1221 <Normal Text></Normal Text><br/>
1222 <Comment>//</Comment><br/>
1223 <Comment>// Match Condition 2</Comment><br/>
1224 <Comment>//</Comment><br/>
1225 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>match_cond2_stb </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr2 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr2 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match_cond2_ct</Normal Text><Symbol>)</Symbol><br/>
1226 <Normal Text> </Normal Text><Keyword>casex</Keyword><Normal Text> </Normal Text><Symbol>({</Symbol><Normal Text>match_cond2_stb</Normal Text><Symbol>,</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CC</Preprocessor><Symbol>]})</Symbol><br/>
1227 <Normal Text> </Normal Text><Binary>4'b0_xxx</Binary><Symbol>,</Symbol><br/>
1228 <Normal Text> </Normal Text><Binary>4'b1_000</Binary><Symbol>,</Symbol><br/>
1229 <Normal Text> </Normal Text><Binary>4'b1_111</Binary><Symbol>:</Symbol><Normal Text> match2 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1230 <Normal Text> </Normal Text><Binary>4'b1_001</Binary><Symbol>:</Symbol><Normal Text> match2 </Normal Text><Symbol>=</Symbol><br/>
1231 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><br/>
1232 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr2</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr2</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1233 <Normal Text> </Normal Text><Binary>4'b1_010</Binary><Symbol>:</Symbol><Normal Text> match2 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1234 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><</Symbol><br/>
1235 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr2</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr2</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1236 <Normal Text> </Normal Text><Binary>4'b1_011</Binary><Symbol>:</Symbol><Normal Text> match2 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1237 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><br/>
1238 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr2</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr2</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1239 <Normal Text> </Normal Text><Binary>4'b1_100</Binary><Symbol>:</Symbol><Normal Text> match2 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1240 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>></Symbol><br/>
1241 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr2</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr2</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1242 <Normal Text> </Normal Text><Binary>4'b1_101</Binary><Symbol>:</Symbol><Normal Text> match2 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1243 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>>=</Symbol><br/>
1244 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr2</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr2</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1245 <Normal Text> </Normal Text><Binary>4'b1_110</Binary><Symbol>:</Symbol><Normal Text> match2 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1246 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond2_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>!=</Symbol><br/>
1247 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr2</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr2</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1248 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1249 <Normal Text></Normal Text><br/>
1250 <Comment>//</Comment><br/>
1251 <Comment>// Watchpoint 2</Comment><br/>
1252 <Comment>//</Comment><br/>
1253 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match2 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
1254 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW2</Preprocessor><Symbol>])</Symbol><br/>
1255 <Normal Text> </Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>2</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match2</Normal Text><Symbol>;</Symbol><br/>
1256 <Normal Text> </Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>2</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match2 </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>1</Integer><Symbol>];</Symbol><br/>
1257 <Normal Text> </Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>2</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match2 </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>1</Integer><Symbol>];</Symbol><br/>
1258 <Normal Text> </Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>2</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1259 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1260 <Normal Text></Normal Text><br/>
1261 <Comment>//</Comment><br/>
1262 <Comment>// Compare To What (Match Condition 3)</Comment><br/>
1263 <Comment>//</Comment><br/>
1264 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr3 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> id_pc </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_adr_i </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_dc</Normal Text><br/>
1265 <Normal Text> </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_lsu </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_we_i</Normal Text><Symbol>)</Symbol><br/>
1266 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Comment>// synopsys parallel_case</Comment><br/>
1267 <Normal Text> </Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text> match_cond3_ct </Normal Text><Symbol>=</Symbol><Normal Text> id_pc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// insn fetch EA</Comment><br/>
1268 <Normal Text> </Normal Text><Binary>3'b010</Binary><Symbol>:</Symbol><Normal Text> match_cond3_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load EA</Comment><br/>
1269 <Normal Text> </Normal Text><Binary>3'b011</Binary><Symbol>:</Symbol><Normal Text> match_cond3_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// store EA</Comment><br/>
1270 <Normal Text> </Normal Text><Binary>3'b100</Binary><Symbol>:</Symbol><Normal Text> match_cond3_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load data</Comment><br/>
1271 <Normal Text> </Normal Text><Binary>3'b101</Binary><Symbol>:</Symbol><Normal Text> match_cond3_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// store data</Comment><br/>
1272 <Normal Text> </Normal Text><Binary>3'b110</Binary><Symbol>:</Symbol><Normal Text> match_cond3_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load/store EA</Comment><br/>
1273 <Normal Text> </Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond3_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_we_i </Normal Text><Symbol>?</Symbol><Normal Text> dcpu_dat_lsu </Normal Text><Symbol>:</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><br/>
1274 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1275 <Normal Text></Normal Text><br/>
1276 <Comment>//</Comment><br/>
1277 <Comment>// When To Compare (Match Condition 3)</Comment><br/>
1278 <Comment>//</Comment><br/>
1279 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr3 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>)</Symbol><br/>
1280 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Comment>// synopsys parallel_case</Comment><br/>
1281 <Normal Text> </Normal Text><Binary>3'b000</Binary><Symbol>:</Symbol><Normal Text> match_cond3_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>//comparison disabled</Comment><br/>
1282 <Normal Text> </Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text> match_cond3_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// insn fetch EA</Comment><br/>
1283 <Normal Text> </Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond3_stb </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// any load/store</Comment><br/>
1284 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1285 <Normal Text></Normal Text><br/>
1286 <Comment>//</Comment><br/>
1287 <Comment>// Match Condition 3</Comment><br/>
1288 <Comment>//</Comment><br/>
1289 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>match_cond3_stb </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr3 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr3 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match_cond3_ct</Normal Text><Symbol>)</Symbol><br/>
1290 <Normal Text> </Normal Text><Keyword>casex</Keyword><Normal Text> </Normal Text><Symbol>({</Symbol><Normal Text>match_cond3_stb</Normal Text><Symbol>,</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CC</Preprocessor><Symbol>]})</Symbol><br/>
1291 <Normal Text> </Normal Text><Binary>4'b0_xxx</Binary><Symbol>,</Symbol><br/>
1292 <Normal Text> </Normal Text><Binary>4'b1_000</Binary><Symbol>,</Symbol><br/>
1293 <Normal Text> </Normal Text><Binary>4'b1_111</Binary><Symbol>:</Symbol><Normal Text> match3 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1294 <Normal Text> </Normal Text><Binary>4'b1_001</Binary><Symbol>:</Symbol><Normal Text> match3 </Normal Text><Symbol>=</Symbol><br/>
1295 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><br/>
1296 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr3</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr3</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1297 <Normal Text> </Normal Text><Binary>4'b1_010</Binary><Symbol>:</Symbol><Normal Text> match3 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1298 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><</Symbol><br/>
1299 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr3</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr3</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1300 <Normal Text> </Normal Text><Binary>4'b1_011</Binary><Symbol>:</Symbol><Normal Text> match3 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1301 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><br/>
1302 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr3</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr3</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1303 <Normal Text> </Normal Text><Binary>4'b1_100</Binary><Symbol>:</Symbol><Normal Text> match3 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1304 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>></Symbol><br/>
1305 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr3</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr3</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1306 <Normal Text> </Normal Text><Binary>4'b1_101</Binary><Symbol>:</Symbol><Normal Text> match3 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1307 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>>=</Symbol><br/>
1308 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr3</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr3</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1309 <Normal Text> </Normal Text><Binary>4'b1_110</Binary><Symbol>:</Symbol><Normal Text> match3 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1310 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond3_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>!=</Symbol><br/>
1311 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr3</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr3</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr3</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1312 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1313 <Normal Text></Normal Text><br/>
1314 <Comment>//</Comment><br/>
1315 <Comment>// Watchpoint 3</Comment><br/>
1316 <Comment>//</Comment><br/>
1317 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match3 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
1318 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW3</Preprocessor><Symbol>])</Symbol><br/>
1319 <Normal Text> </Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>3</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match3</Normal Text><Symbol>;</Symbol><br/>
1320 <Normal Text> </Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>3</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match3 </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>2</Integer><Symbol>];</Symbol><br/>
1321 <Normal Text> </Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>3</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match3 </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>2</Integer><Symbol>];</Symbol><br/>
1322 <Normal Text> </Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>3</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1323 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1324 <Normal Text></Normal Text><br/>
1325 <Comment>//</Comment><br/>
1326 <Comment>// Compare To What (Match Condition 4)</Comment><br/>
1327 <Comment>//</Comment><br/>
1328 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr4 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> id_pc </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_adr_i </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_dc</Normal Text><br/>
1329 <Normal Text> </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_lsu </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_we_i</Normal Text><Symbol>)</Symbol><br/>
1330 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Comment>// synopsys parallel_case</Comment><br/>
1331 <Normal Text> </Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text> match_cond4_ct </Normal Text><Symbol>=</Symbol><Normal Text> id_pc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// insn fetch EA</Comment><br/>
1332 <Normal Text> </Normal Text><Binary>3'b010</Binary><Symbol>:</Symbol><Normal Text> match_cond4_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load EA</Comment><br/>
1333 <Normal Text> </Normal Text><Binary>3'b011</Binary><Symbol>:</Symbol><Normal Text> match_cond4_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// store EA</Comment><br/>
1334 <Normal Text> </Normal Text><Binary>3'b100</Binary><Symbol>:</Symbol><Normal Text> match_cond4_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load data</Comment><br/>
1335 <Normal Text> </Normal Text><Binary>3'b101</Binary><Symbol>:</Symbol><Normal Text> match_cond4_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// store data</Comment><br/>
1336 <Normal Text> </Normal Text><Binary>3'b110</Binary><Symbol>:</Symbol><Normal Text> match_cond4_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load/store EA</Comment><br/>
1337 <Normal Text> </Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond4_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_we_i </Normal Text><Symbol>?</Symbol><Normal Text> dcpu_dat_lsu </Normal Text><Symbol>:</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><br/>
1338 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1339 <Normal Text></Normal Text><br/>
1340 <Comment>//</Comment><br/>
1341 <Comment>// When To Compare (Match Condition 4)</Comment><br/>
1342 <Comment>//</Comment><br/>
1343 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr4 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>)</Symbol><br/>
1344 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Comment>// synopsys parallel_case</Comment><br/>
1345 <Normal Text> </Normal Text><Binary>3'b000</Binary><Symbol>:</Symbol><Normal Text> match_cond4_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>//comparison disabled</Comment><br/>
1346 <Normal Text> </Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text> match_cond4_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// insn fetch EA</Comment><br/>
1347 <Normal Text> </Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond4_stb </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// any load/store</Comment><br/>
1348 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1349 <Normal Text></Normal Text><br/>
1350 <Comment>//</Comment><br/>
1351 <Comment>// Match Condition 4</Comment><br/>
1352 <Comment>//</Comment><br/>
1353 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>match_cond4_stb </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr4 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr4 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match_cond4_ct</Normal Text><Symbol>)</Symbol><br/>
1354 <Normal Text> </Normal Text><Keyword>casex</Keyword><Normal Text> </Normal Text><Symbol>({</Symbol><Normal Text>match_cond4_stb</Normal Text><Symbol>,</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CC</Preprocessor><Symbol>]})</Symbol><br/>
1355 <Normal Text> </Normal Text><Binary>4'b0_xxx</Binary><Symbol>,</Symbol><br/>
1356 <Normal Text> </Normal Text><Binary>4'b1_000</Binary><Symbol>,</Symbol><br/>
1357 <Normal Text> </Normal Text><Binary>4'b1_111</Binary><Symbol>:</Symbol><Normal Text> match4 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1358 <Normal Text> </Normal Text><Binary>4'b1_001</Binary><Symbol>:</Symbol><Normal Text> match4 </Normal Text><Symbol>=</Symbol><br/>
1359 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><br/>
1360 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr4</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr4</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1361 <Normal Text> </Normal Text><Binary>4'b1_010</Binary><Symbol>:</Symbol><Normal Text> match4 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1362 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><</Symbol><br/>
1363 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr4</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr4</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1364 <Normal Text> </Normal Text><Binary>4'b1_011</Binary><Symbol>:</Symbol><Normal Text> match4 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1365 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><br/>
1366 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr4</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr4</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1367 <Normal Text> </Normal Text><Binary>4'b1_100</Binary><Symbol>:</Symbol><Normal Text> match4 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1368 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>></Symbol><br/>
1369 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr4</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr4</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1370 <Normal Text> </Normal Text><Binary>4'b1_101</Binary><Symbol>:</Symbol><Normal Text> match4 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1371 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>>=</Symbol><br/>
1372 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr4</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr4</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1373 <Normal Text> </Normal Text><Binary>4'b1_110</Binary><Symbol>:</Symbol><Normal Text> match4 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1374 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond4_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>!=</Symbol><br/>
1375 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr4</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr4</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr4</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1376 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1377 <Normal Text></Normal Text><br/>
1378 <Comment>//</Comment><br/>
1379 <Comment>// Watchpoint 4</Comment><br/>
1380 <Comment>//</Comment><br/>
1381 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match4 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
1382 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW4</Preprocessor><Symbol>])</Symbol><br/>
1383 <Normal Text> </Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>4</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match4</Normal Text><Symbol>;</Symbol><br/>
1384 <Normal Text> </Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>4</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match4 </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>3</Integer><Symbol>];</Symbol><br/>
1385 <Normal Text> </Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>4</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match4 </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>3</Integer><Symbol>];</Symbol><br/>
1386 <Normal Text> </Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>4</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1387 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1388 <Normal Text></Normal Text><br/>
1389 <Comment>//</Comment><br/>
1390 <Comment>// Compare To What (Match Condition 5)</Comment><br/>
1391 <Comment>//</Comment><br/>
1392 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr5 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> id_pc </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_adr_i </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_dc</Normal Text><br/>
1393 <Normal Text> </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_lsu </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_we_i</Normal Text><Symbol>)</Symbol><br/>
1394 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Comment>// synopsys parallel_case</Comment><br/>
1395 <Normal Text> </Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text> match_cond5_ct </Normal Text><Symbol>=</Symbol><Normal Text> id_pc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// insn fetch EA</Comment><br/>
1396 <Normal Text> </Normal Text><Binary>3'b010</Binary><Symbol>:</Symbol><Normal Text> match_cond5_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load EA</Comment><br/>
1397 <Normal Text> </Normal Text><Binary>3'b011</Binary><Symbol>:</Symbol><Normal Text> match_cond5_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// store EA</Comment><br/>
1398 <Normal Text> </Normal Text><Binary>3'b100</Binary><Symbol>:</Symbol><Normal Text> match_cond5_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load data</Comment><br/>
1399 <Normal Text> </Normal Text><Binary>3'b101</Binary><Symbol>:</Symbol><Normal Text> match_cond5_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// store data</Comment><br/>
1400 <Normal Text> </Normal Text><Binary>3'b110</Binary><Symbol>:</Symbol><Normal Text> match_cond5_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load/store EA</Comment><br/>
1401 <Normal Text> </Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond5_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_we_i </Normal Text><Symbol>?</Symbol><Normal Text> dcpu_dat_lsu </Normal Text><Symbol>:</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><br/>
1402 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1403 <Normal Text></Normal Text><br/>
1404 <Comment>//</Comment><br/>
1405 <Comment>// When To Compare (Match Condition 5)</Comment><br/>
1406 <Comment>//</Comment><br/>
1407 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr5 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>)</Symbol><br/>
1408 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Comment>// synopsys parallel_case</Comment><br/>
1409 <Normal Text> </Normal Text><Binary>3'b000</Binary><Symbol>:</Symbol><Normal Text> match_cond5_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>//comparison disabled</Comment><br/>
1410 <Normal Text> </Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text> match_cond5_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// insn fetch EA</Comment><br/>
1411 <Normal Text> </Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond5_stb </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// any load/store</Comment><br/>
1412 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1413 <Normal Text></Normal Text><br/>
1414 <Comment>//</Comment><br/>
1415 <Comment>// Match Condition 5</Comment><br/>
1416 <Comment>//</Comment><br/>
1417 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>match_cond5_stb </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr5 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr5 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match_cond5_ct</Normal Text><Symbol>)</Symbol><br/>
1418 <Normal Text> </Normal Text><Keyword>casex</Keyword><Normal Text> </Normal Text><Symbol>({</Symbol><Normal Text>match_cond5_stb</Normal Text><Symbol>,</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CC</Preprocessor><Symbol>]})</Symbol><br/>
1419 <Normal Text> </Normal Text><Binary>4'b0_xxx</Binary><Symbol>,</Symbol><br/>
1420 <Normal Text> </Normal Text><Binary>4'b1_000</Binary><Symbol>,</Symbol><br/>
1421 <Normal Text> </Normal Text><Binary>4'b1_111</Binary><Symbol>:</Symbol><Normal Text> match5 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1422 <Normal Text> </Normal Text><Binary>4'b1_001</Binary><Symbol>:</Symbol><Normal Text> match5 </Normal Text><Symbol>=</Symbol><br/>
1423 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><br/>
1424 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr5</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr5</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1425 <Normal Text> </Normal Text><Binary>4'b1_010</Binary><Symbol>:</Symbol><Normal Text> match5 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1426 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><</Symbol><br/>
1427 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr5</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr5</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1428 <Normal Text> </Normal Text><Binary>4'b1_011</Binary><Symbol>:</Symbol><Normal Text> match5 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1429 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><br/>
1430 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr5</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr5</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1431 <Normal Text> </Normal Text><Binary>4'b1_100</Binary><Symbol>:</Symbol><Normal Text> match5 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1432 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>></Symbol><br/>
1433 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr5</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr5</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1434 <Normal Text> </Normal Text><Binary>4'b1_101</Binary><Symbol>:</Symbol><Normal Text> match5 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1435 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>>=</Symbol><br/>
1436 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr5</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr5</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1437 <Normal Text> </Normal Text><Binary>4'b1_110</Binary><Symbol>:</Symbol><Normal Text> match5 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1438 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond5_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>!=</Symbol><br/>
1439 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr5</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr5</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr5</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1440 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1441 <Normal Text></Normal Text><br/>
1442 <Comment>//</Comment><br/>
1443 <Comment>// Watchpoint 5</Comment><br/>
1444 <Comment>//</Comment><br/>
1445 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match5 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
1446 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW5</Preprocessor><Symbol>])</Symbol><br/>
1447 <Normal Text> </Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>5</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match5</Normal Text><Symbol>;</Symbol><br/>
1448 <Normal Text> </Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>5</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match5 </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>4</Integer><Symbol>];</Symbol><br/>
1449 <Normal Text> </Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>5</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match5 </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>4</Integer><Symbol>];</Symbol><br/>
1450 <Normal Text> </Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>5</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1451 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1452 <Normal Text></Normal Text><br/>
1453 <Comment>//</Comment><br/>
1454 <Comment>// Compare To What (Match Condition 6)</Comment><br/>
1455 <Comment>//</Comment><br/>
1456 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr6 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> id_pc </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_adr_i </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_dc</Normal Text><br/>
1457 <Normal Text> </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_lsu </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_we_i</Normal Text><Symbol>)</Symbol><br/>
1458 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Comment>// synopsys parallel_case</Comment><br/>
1459 <Normal Text> </Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text> match_cond6_ct </Normal Text><Symbol>=</Symbol><Normal Text> id_pc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// insn fetch EA</Comment><br/>
1460 <Normal Text> </Normal Text><Binary>3'b010</Binary><Symbol>:</Symbol><Normal Text> match_cond6_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load EA</Comment><br/>
1461 <Normal Text> </Normal Text><Binary>3'b011</Binary><Symbol>:</Symbol><Normal Text> match_cond6_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// store EA</Comment><br/>
1462 <Normal Text> </Normal Text><Binary>3'b100</Binary><Symbol>:</Symbol><Normal Text> match_cond6_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load data</Comment><br/>
1463 <Normal Text> </Normal Text><Binary>3'b101</Binary><Symbol>:</Symbol><Normal Text> match_cond6_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// store data</Comment><br/>
1464 <Normal Text> </Normal Text><Binary>3'b110</Binary><Symbol>:</Symbol><Normal Text> match_cond6_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load/store EA</Comment><br/>
1465 <Normal Text> </Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond6_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_we_i </Normal Text><Symbol>?</Symbol><Normal Text> dcpu_dat_lsu </Normal Text><Symbol>:</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><br/>
1466 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1467 <Normal Text></Normal Text><br/>
1468 <Comment>//</Comment><br/>
1469 <Comment>// When To Compare (Match Condition 6)</Comment><br/>
1470 <Comment>//</Comment><br/>
1471 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr6 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>)</Symbol><br/>
1472 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Comment>// synopsys parallel_case</Comment><br/>
1473 <Normal Text> </Normal Text><Binary>3'b000</Binary><Symbol>:</Symbol><Normal Text> match_cond6_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>//comparison disabled</Comment><br/>
1474 <Normal Text> </Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text> match_cond6_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// insn fetch EA</Comment><br/>
1475 <Normal Text> </Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond6_stb </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// any load/store</Comment><br/>
1476 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1477 <Normal Text></Normal Text><br/>
1478 <Comment>//</Comment><br/>
1479 <Comment>// Match Condition 6</Comment><br/>
1480 <Comment>//</Comment><br/>
1481 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>match_cond6_stb </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr6 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr6 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match_cond6_ct</Normal Text><Symbol>)</Symbol><br/>
1482 <Normal Text> </Normal Text><Keyword>casex</Keyword><Normal Text> </Normal Text><Symbol>({</Symbol><Normal Text>match_cond6_stb</Normal Text><Symbol>,</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CC</Preprocessor><Symbol>]})</Symbol><br/>
1483 <Normal Text> </Normal Text><Binary>4'b0_xxx</Binary><Symbol>,</Symbol><br/>
1484 <Normal Text> </Normal Text><Binary>4'b1_000</Binary><Symbol>,</Symbol><br/>
1485 <Normal Text> </Normal Text><Binary>4'b1_111</Binary><Symbol>:</Symbol><Normal Text> match6 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1486 <Normal Text> </Normal Text><Binary>4'b1_001</Binary><Symbol>:</Symbol><Normal Text> match6 </Normal Text><Symbol>=</Symbol><br/>
1487 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><br/>
1488 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr6</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr6</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1489 <Normal Text> </Normal Text><Binary>4'b1_010</Binary><Symbol>:</Symbol><Normal Text> match6 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1490 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><</Symbol><br/>
1491 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr6</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr6</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1492 <Normal Text> </Normal Text><Binary>4'b1_011</Binary><Symbol>:</Symbol><Normal Text> match6 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1493 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><br/>
1494 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr6</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr6</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1495 <Normal Text> </Normal Text><Binary>4'b1_100</Binary><Symbol>:</Symbol><Normal Text> match6 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1496 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>></Symbol><br/>
1497 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr6</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr6</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1498 <Normal Text> </Normal Text><Binary>4'b1_101</Binary><Symbol>:</Symbol><Normal Text> match6 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1499 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>>=</Symbol><br/>
1500 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr6</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr6</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1501 <Normal Text> </Normal Text><Binary>4'b1_110</Binary><Symbol>:</Symbol><Normal Text> match6 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1502 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond6_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>!=</Symbol><br/>
1503 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr6</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr6</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr6</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1504 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1505 <Normal Text></Normal Text><br/>
1506 <Comment>//</Comment><br/>
1507 <Comment>// Watchpoint 6</Comment><br/>
1508 <Comment>//</Comment><br/>
1509 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match6 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
1510 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW6</Preprocessor><Symbol>])</Symbol><br/>
1511 <Normal Text> </Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>6</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match6</Normal Text><Symbol>;</Symbol><br/>
1512 <Normal Text> </Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>6</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match6 </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>5</Integer><Symbol>];</Symbol><br/>
1513 <Normal Text> </Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>6</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match6 </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>5</Integer><Symbol>];</Symbol><br/>
1514 <Normal Text> </Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>6</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1515 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1516 <Normal Text></Normal Text><br/>
1517 <Comment>//</Comment><br/>
1518 <Comment>// Compare To What (Match Condition 7)</Comment><br/>
1519 <Comment>//</Comment><br/>
1520 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr7 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> id_pc </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_adr_i </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_dc</Normal Text><br/>
1521 <Normal Text> </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_dat_lsu </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_we_i</Normal Text><Symbol>)</Symbol><br/>
1522 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Comment>// synopsys parallel_case</Comment><br/>
1523 <Normal Text> </Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text> match_cond7_ct </Normal Text><Symbol>=</Symbol><Normal Text> id_pc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// insn fetch EA</Comment><br/>
1524 <Normal Text> </Normal Text><Binary>3'b010</Binary><Symbol>:</Symbol><Normal Text> match_cond7_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load EA</Comment><br/>
1525 <Normal Text> </Normal Text><Binary>3'b011</Binary><Symbol>:</Symbol><Normal Text> match_cond7_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// store EA</Comment><br/>
1526 <Normal Text> </Normal Text><Binary>3'b100</Binary><Symbol>:</Symbol><Normal Text> match_cond7_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load data</Comment><br/>
1527 <Normal Text> </Normal Text><Binary>3'b101</Binary><Symbol>:</Symbol><Normal Text> match_cond7_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_dat_lsu</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// store data</Comment><br/>
1528 <Normal Text> </Normal Text><Binary>3'b110</Binary><Symbol>:</Symbol><Normal Text> match_cond7_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_adr_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// load/store EA</Comment><br/>
1529 <Normal Text> </Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond7_ct </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_we_i </Normal Text><Symbol>?</Symbol><Normal Text> dcpu_dat_lsu </Normal Text><Symbol>:</Symbol><Normal Text> dcpu_dat_dc</Normal Text><Symbol>;</Symbol><br/>
1530 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1531 <Normal Text></Normal Text><br/>
1532 <Comment>//</Comment><br/>
1533 <Comment>// When To Compare (Match Condition 7)</Comment><br/>
1534 <Comment>//</Comment><br/>
1535 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dcr7 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>)</Symbol><br/>
1536 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CT</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Comment>// synopsys parallel_case</Comment><br/>
1537 <Normal Text> </Normal Text><Binary>3'b000</Binary><Symbol>:</Symbol><Normal Text> match_cond7_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>//comparison disabled</Comment><br/>
1538 <Normal Text> </Normal Text><Binary>3'b001</Binary><Symbol>:</Symbol><Normal Text> match_cond7_stb </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// insn fetch EA</Comment><br/>
1539 <Normal Text> </Normal Text><Keyword>default</Keyword><Symbol>:</Symbol><Normal Text>match_cond7_stb </Normal Text><Symbol>=</Symbol><Normal Text> dcpu_cycstb_i</Normal Text><Symbol>;</Symbol><Normal Text> </Normal Text><Comment>// any load/store</Comment><br/>
1540 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1541 <Normal Text></Normal Text><br/>
1542 <Comment>//</Comment><br/>
1543 <Comment>// Match Condition 7</Comment><br/>
1544 <Comment>//</Comment><br/>
1545 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>match_cond7_stb </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dcr7 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dvr7 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match_cond7_ct</Normal Text><Symbol>)</Symbol><br/>
1546 <Normal Text> </Normal Text><Keyword>casex</Keyword><Normal Text> </Normal Text><Symbol>({</Symbol><Normal Text>match_cond7_stb</Normal Text><Symbol>,</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_CC</Preprocessor><Symbol>]})</Symbol><br/>
1547 <Normal Text> </Normal Text><Binary>4'b0_xxx</Binary><Symbol>,</Symbol><br/>
1548 <Normal Text> </Normal Text><Binary>4'b1_000</Binary><Symbol>,</Symbol><br/>
1549 <Normal Text> </Normal Text><Binary>4'b1_111</Binary><Symbol>:</Symbol><Normal Text> match7 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1550 <Normal Text> </Normal Text><Binary>4'b1_001</Binary><Symbol>:</Symbol><Normal Text> match7 </Normal Text><Symbol>=</Symbol><br/>
1551 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><br/>
1552 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr7</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr7</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1553 <Normal Text> </Normal Text><Binary>4'b1_010</Binary><Symbol>:</Symbol><Normal Text> match7 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1554 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><</Symbol><br/>
1555 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr7</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr7</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1556 <Normal Text> </Normal Text><Binary>4'b1_011</Binary><Symbol>:</Symbol><Normal Text> match7 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1557 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol><=</Symbol><br/>
1558 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr7</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr7</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1559 <Normal Text> </Normal Text><Binary>4'b1_100</Binary><Symbol>:</Symbol><Normal Text> match7 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1560 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>></Symbol><br/>
1561 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr7</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr7</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1562 <Normal Text> </Normal Text><Binary>4'b1_101</Binary><Symbol>:</Symbol><Normal Text> match7 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1563 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>>=</Symbol><br/>
1564 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr7</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr7</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1565 <Normal Text> </Normal Text><Binary>4'b1_110</Binary><Symbol>:</Symbol><Normal Text> match7 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><br/>
1566 <Normal Text> </Normal Text><Symbol>({(</Symbol><Normal Text>match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> match_cond7_ct</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]}</Symbol><Normal Text> </Normal Text><Symbol>!=</Symbol><br/>
1567 <Normal Text> </Normal Text><Symbol>{(</Symbol><Normal Text>dvr7</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>^</Symbol><Normal Text> dcr7</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DCR_SC</Preprocessor><Symbol>]),</Symbol><Normal Text> dvr7</Normal Text><Symbol>[</Symbol><Integer>30</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]});</Symbol><br/>
1568 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1569 <Normal Text></Normal Text><br/>
1570 <Comment>//</Comment><br/>
1571 <Comment>// Watchpoint 7</Comment><br/>
1572 <Comment>//</Comment><br/>
1573 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> match7 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
1574 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW7</Preprocessor><Symbol>])</Symbol><br/>
1575 <Normal Text> </Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match7</Normal Text><Symbol>;</Symbol><br/>
1576 <Normal Text> </Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match7 </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>6</Integer><Symbol>];</Symbol><br/>
1577 <Normal Text> </Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> match7 </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>6</Integer><Symbol>];</Symbol><br/>
1578 <Normal Text> </Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1579 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1580 <Normal Text></Normal Text><br/>
1581 <Comment>//</Comment><br/>
1582 <Comment>// Increment Watchpoint Counter 0</Comment><br/>
1583 <Comment>//</Comment><br/>
1584 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>wp </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dmr2</Normal Text><Symbol>)</Symbol><br/>
1585 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR2_WCE0</Preprocessor><Symbol>])</Symbol><br/>
1586 <Normal Text> incr_wpcntr0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>|(</Symbol><Normal Text>wp </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>~</Symbol><Normal Text>dmr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR2_AWTC</Preprocessor><Symbol>]);</Symbol><br/>
1587 <Normal Text> </Normal Text><Keyword>else</Keyword><br/>
1588 <Normal Text> incr_wpcntr0 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1589 <Normal Text></Normal Text><br/>
1590 <Comment>//</Comment><br/>
1591 <Comment>// Match Condition Watchpoint Counter 0</Comment><br/>
1592 <Comment>//</Comment><br/>
1593 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dwcr0</Normal Text><Symbol>)</Symbol><br/>
1594 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dwcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DWCR_MATCH</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> dwcr0</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DWCR_COUNT</Preprocessor><Symbol>])</Symbol><br/>
1595 <Normal Text> wpcntr0_match </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
1596 <Normal Text> </Normal Text><Keyword>else</Keyword><br/>
1597 <Normal Text> wpcntr0_match </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1598 <Normal Text></Normal Text><br/>
1599 <Normal Text></Normal Text><br/>
1600 <Comment>//</Comment><br/>
1601 <Comment>// Watchpoint 8</Comment><br/>
1602 <Comment>//</Comment><br/>
1603 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wpcntr0_match </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
1604 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW8</Preprocessor><Symbol>])</Symbol><br/>
1605 <Normal Text> </Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>8</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> wpcntr0_match</Normal Text><Symbol>;</Symbol><br/>
1606 <Normal Text> </Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>8</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> wpcntr0_match </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>];</Symbol><br/>
1607 <Normal Text> </Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>8</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> wpcntr0_match </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>];</Symbol><br/>
1608 <Normal Text> </Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>8</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1609 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1610 <Normal Text></Normal Text><br/>
1611 <Normal Text></Normal Text><br/>
1612 <Comment>//</Comment><br/>
1613 <Comment>// Increment Watchpoint Counter 1</Comment><br/>
1614 <Comment>//</Comment><br/>
1615 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>wp </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dmr2</Normal Text><Symbol>)</Symbol><br/>
1616 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR2_WCE1</Preprocessor><Symbol>])</Symbol><br/>
1617 <Normal Text> incr_wpcntr1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>|(</Symbol><Normal Text>wp </Normal Text><Symbol>&</Symbol><Normal Text> dmr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR2_AWTC</Preprocessor><Symbol>]);</Symbol><br/>
1618 <Normal Text> </Normal Text><Keyword>else</Keyword><br/>
1619 <Normal Text> incr_wpcntr1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1620 <Normal Text></Normal Text><br/>
1621 <Comment>//</Comment><br/>
1622 <Comment>// Match Condition Watchpoint Counter 1</Comment><br/>
1623 <Comment>//</Comment><br/>
1624 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dwcr1</Normal Text><Symbol>)</Symbol><br/>
1625 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dwcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DWCR_MATCH</Preprocessor><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> dwcr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DWCR_COUNT</Preprocessor><Symbol>])</Symbol><br/>
1626 <Normal Text> wpcntr1_match </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
1627 <Normal Text> </Normal Text><Keyword>else</Keyword><br/>
1628 <Normal Text> wpcntr1_match </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1629 <Normal Text></Normal Text><br/>
1630 <Comment>//</Comment><br/>
1631 <Comment>// Watchpoint 9</Comment><br/>
1632 <Comment>//</Comment><br/>
1633 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wpcntr1_match </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
1634 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW9</Preprocessor><Symbol>])</Symbol><br/>
1635 <Normal Text> </Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>9</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> wpcntr1_match</Normal Text><Symbol>;</Symbol><br/>
1636 <Normal Text> </Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>9</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> wpcntr1_match </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>8</Integer><Symbol>];</Symbol><br/>
1637 <Normal Text> </Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>9</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> wpcntr1_match </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>8</Integer><Symbol>];</Symbol><br/>
1638 <Normal Text> </Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>9</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1639 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1640 <Normal Text></Normal Text><br/>
1641 <Comment>//</Comment><br/>
1642 <Comment>// Watchpoint 10</Comment><br/>
1643 <Comment>//</Comment><br/>
1644 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Normal Text>dmr1 </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> dbg_ewt_i </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> wp</Normal Text><Symbol>)</Symbol><br/>
1645 <Normal Text> </Normal Text><Keyword>case</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dmr1</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR1_CW10</Preprocessor><Symbol>])</Symbol><br/>
1646 <Normal Text> </Normal Text><Binary>2'b00</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>10</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> dbg_ewt_i</Normal Text><Symbol>;</Symbol><br/>
1647 <Normal Text> </Normal Text><Binary>2'b01</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>10</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> dbg_ewt_i </Normal Text><Symbol>&</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>9</Integer><Symbol>];</Symbol><br/>
1648 <Normal Text> </Normal Text><Binary>2'b10</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>10</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> dbg_ewt_i </Normal Text><Symbol>|</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>9</Integer><Symbol>];</Symbol><br/>
1649 <Normal Text> </Normal Text><Binary>2'b11</Binary><Symbol>:</Symbol><Normal Text> wp</Normal Text><Symbol>[</Symbol><Integer>10</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1650 <Normal Text> </Normal Text><Keyword>endcase</Keyword><br/>
1651 <Normal Text></Normal Text><br/>
1652 <Preprocessor>`endif</Preprocessor><br/>
1653 <Normal Text></Normal Text><br/>
1654 <Comment>//</Comment><br/>
1655 <Comment>// Watchpoints can cause trap exception</Comment><br/>
1656 <Comment>//</Comment><br/>
1657 <Preprocessor>`ifdef OR1200_DU_HWBKPTS</Preprocessor><br/>
1658 <Keyword>assign</Keyword><Normal Text> du_hwbkpt </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>|(</Symbol><Normal Text>wp </Normal Text><Symbol>&</Symbol><Normal Text> dmr2</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DMR2_WGB</Preprocessor><Symbol>])</Symbol><Normal Text> </Normal Text><Symbol>|</Symbol><Normal Text> du_hwbkpt_hold </Normal Text><Symbol>|</Symbol><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>dbg_bp_r </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>~</Symbol><Normal Text>dsr</Normal Text><Symbol>[</Symbol><Preprocessor>`OR1200_DU_DSR_TE</Preprocessor><Symbol>]);</Symbol><br/>
1659 <Preprocessor>`else</Preprocessor><br/>
1660 <Keyword>assign</Keyword><Normal Text> du_hwbkpt </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1661 <Preprocessor>`endif</Preprocessor><br/>
1662 <Normal Text></Normal Text><br/>
1663 <Comment>// Hold du_hwbkpt if ex_freeze is active in order to cause trap exception </Comment><br/>
1664 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
1665 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
1666 <Normal Text> du_hwbkpt_hold </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1667 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>du_hwbkpt </Normal Text><Symbol>&</Symbol><Normal Text> ex_freeze</Normal Text><Symbol>)</Symbol><br/>
1668 <Normal Text> du_hwbkpt_hold </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b1</Binary><Symbol>;</Symbol><br/>
1669 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(!</Symbol><Normal Text>ex_freeze</Normal Text><Symbol>)</Symbol><br/>
1670 <Normal Text> du_hwbkpt_hold </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1671 <Normal Text></Normal Text><br/>
1672 <Preprocessor>`ifdef OR1200_DU_TB_IMPLEMENTED</Preprocessor><br/>
1673 <Comment>//</Comment><br/>
1674 <Comment>// Simple trace buffer</Comment><br/>
1675 <Comment>// (right now hardcoded for Xilinx Virtex FPGAs)</Comment><br/>
1676 <Comment>//</Comment><br/>
1677 <Comment>// Stores last 256 instruction addresses, instruction</Comment><br/>
1678 <Comment>// machine words and ALU results</Comment><br/>
1679 <Comment>//</Comment><br/>
1680 <Normal Text></Normal Text><br/>
1681 <Comment>//</Comment><br/>
1682 <Comment>// Trace buffer write enable</Comment><br/>
1683 <Comment>//</Comment><br/>
1684 <Keyword>assign</Keyword><Normal Text> tb_enw </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>~</Symbol><Normal Text>ex_freeze </Normal Text><Symbol>&</Symbol><Normal Text> </Normal Text><Symbol>~((</Symbol><Normal Text>ex_insn</Normal Text><Symbol>[</Symbol><Integer>31</Integer><Symbol>:</Symbol><Integer>26</Integer><Symbol>]</Symbol><Normal Text> </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_OR32_NOP</Preprocessor><Symbol>)</Symbol><Normal Text> </Normal Text><Symbol>&</Symbol><Normal Text> ex_insn</Normal Text><Symbol>[</Symbol><Integer>16</Integer><Symbol>]);</Symbol><br/>
1685 <Normal Text></Normal Text><br/>
1686 <Comment>//</Comment><br/>
1687 <Comment>// Trace buffer write address pointer</Comment><br/>
1688 <Comment>//</Comment><br/>
1689 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
1690 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
1691 <Normal Text> tb_wadr </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>8'h00</Hex><Symbol>;</Symbol><br/>
1692 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>tb_enw</Normal Text><Symbol>)</Symbol><br/>
1693 <Normal Text> tb_wadr </Normal Text><Symbol><=</Symbol><Normal Text> tb_wadr </Normal Text><Symbol>+</Symbol><Normal Text> </Normal Text><Decimal>8'd1</Decimal><Symbol>;</Symbol><br/>
1694 <Normal Text></Normal Text><br/>
1695 <Comment>//</Comment><br/>
1696 <Comment>// Free running counter (time stamp)</Comment><br/>
1697 <Comment>//</Comment><br/>
1698 <Keyword>always</Keyword><Normal Text> </Normal Text><Symbol>@(</Symbol><Keyword>posedge</Keyword><Normal Text> clk </Normal Text><Gate instantiation>or</Gate instantiation><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_EVENT</Preprocessor><Normal Text> rst</Normal Text><Symbol>)</Symbol><br/>
1699 <Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(</Symbol><Normal Text>rst </Normal Text><Symbol>==</Symbol><Normal Text> </Normal Text><Preprocessor>`OR1200_RST_VALUE</Preprocessor><Symbol>)</Symbol><br/>
1700 <Normal Text> tb_timstmp </Normal Text><Symbol><=</Symbol><Normal Text> </Normal Text><Hex>32'h00000000</Hex><Symbol>;</Symbol><br/>
1701 <Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Keyword>if</Keyword><Normal Text> </Normal Text><Symbol>(!</Symbol><Normal Text>dbg_bp_r</Normal Text><Symbol>)</Symbol><br/>
1702 <Normal Text> tb_timstmp </Normal Text><Symbol><=</Symbol><Normal Text> tb_timstmp </Normal Text><Symbol>+</Symbol><Normal Text> </Normal Text><Decimal>32'd1</Decimal><Symbol>;</Symbol><br/>
1703 <Normal Text></Normal Text><br/>
1704 <Comment>//</Comment><br/>
1705 <Comment>// Trace buffer RAMs</Comment><br/>
1706 <Comment>//</Comment><br/>
1707 <Normal Text></Normal Text><br/>
1708 <Normal Text>or1200_dpram_256x32 tbia_ram</Normal Text><Symbol>(</Symbol><br/>
1709 <Normal Text> .clk_a</Normal Text><Symbol>(</Symbol><Normal Text>clk</Normal Text><Symbol>),</Symbol><br/>
1710 <Normal Text> .rst_a</Normal Text><Symbol>(</Symbol><Binary>1'b0</Binary><Symbol>),</Symbol><br/>
1711 <Normal Text> .addr_a</Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]),</Symbol><br/>
1712 <Normal Text> .ce_a</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
1713 <Normal Text> .oe_a</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
1714 <Normal Text> .do_a</Normal Text><Symbol>(</Symbol><Normal Text>tbia_dat_o</Normal Text><Symbol>),</Symbol><br/>
1715 <Normal Text></Normal Text><br/>
1716 <Normal Text> .clk_b</Normal Text><Symbol>(</Symbol><Normal Text>clk</Normal Text><Symbol>),</Symbol><br/>
1717 <Normal Text> .rst_b</Normal Text><Symbol>(</Symbol><Binary>1'b0</Binary><Symbol>),</Symbol><br/>
1718 <Normal Text> .addr_b</Normal Text><Symbol>(</Symbol><Normal Text>tb_wadr</Normal Text><Symbol>),</Symbol><br/>
1719 <Normal Text> .di_b</Normal Text><Symbol>(</Symbol><Normal Text>spr_dat_npc</Normal Text><Symbol>),</Symbol><br/>
1720 <Normal Text> .ce_b</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
1721 <Normal Text> .we_b</Normal Text><Symbol>(</Symbol><Normal Text>tb_enw</Normal Text><Symbol>)</Symbol><br/>
1722 <Normal Text></Normal Text><br/>
1723 <Symbol>);</Symbol><br/>
1724 <Normal Text></Normal Text><br/>
1725 <Normal Text>or1200_dpram_256x32 tbim_ram</Normal Text><Symbol>(</Symbol><br/>
1726 <Normal Text> .clk_a</Normal Text><Symbol>(</Symbol><Normal Text>clk</Normal Text><Symbol>),</Symbol><br/>
1727 <Normal Text> .rst_a</Normal Text><Symbol>(</Symbol><Binary>1'b0</Binary><Symbol>),</Symbol><br/>
1728 <Normal Text> .addr_a</Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]),</Symbol><br/>
1729 <Normal Text> .ce_a</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
1730 <Normal Text> .oe_a</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
1731 <Normal Text> .do_a</Normal Text><Symbol>(</Symbol><Normal Text>tbim_dat_o</Normal Text><Symbol>),</Symbol><br/>
1732 <Normal Text> </Normal Text><br/>
1733 <Normal Text> .clk_b</Normal Text><Symbol>(</Symbol><Normal Text>clk</Normal Text><Symbol>),</Symbol><br/>
1734 <Normal Text> .rst_b</Normal Text><Symbol>(</Symbol><Binary>1'b0</Binary><Symbol>),</Symbol><br/>
1735 <Normal Text> .addr_b</Normal Text><Symbol>(</Symbol><Normal Text>tb_wadr</Normal Text><Symbol>),</Symbol><br/>
1736 <Normal Text> .di_b</Normal Text><Symbol>(</Symbol><Normal Text>ex_insn</Normal Text><Symbol>),</Symbol><br/>
1737 <Normal Text> .ce_b</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
1738 <Normal Text> .we_b</Normal Text><Symbol>(</Symbol><Normal Text>tb_enw</Normal Text><Symbol>)</Symbol><br/>
1739 <Symbol>);</Symbol><br/>
1740 <Normal Text></Normal Text><br/>
1741 <Normal Text>or1200_dpram_256x32 tbar_ram</Normal Text><Symbol>(</Symbol><br/>
1742 <Normal Text> .clk_a</Normal Text><Symbol>(</Symbol><Normal Text>clk</Normal Text><Symbol>),</Symbol><br/>
1743 <Normal Text> .rst_a</Normal Text><Symbol>(</Symbol><Binary>1'b0</Binary><Symbol>),</Symbol><br/>
1744 <Normal Text> .addr_a</Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]),</Symbol><br/>
1745 <Normal Text> .ce_a</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
1746 <Normal Text> .oe_a</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
1747 <Normal Text> .do_a</Normal Text><Symbol>(</Symbol><Normal Text>tbar_dat_o</Normal Text><Symbol>),</Symbol><br/>
1748 <Normal Text> </Normal Text><br/>
1749 <Normal Text> .clk_b</Normal Text><Symbol>(</Symbol><Normal Text>clk</Normal Text><Symbol>),</Symbol><br/>
1750 <Normal Text> .rst_b</Normal Text><Symbol>(</Symbol><Binary>1'b0</Binary><Symbol>),</Symbol><br/>
1751 <Normal Text> .addr_b</Normal Text><Symbol>(</Symbol><Normal Text>tb_wadr</Normal Text><Symbol>),</Symbol><br/>
1752 <Normal Text> .di_b</Normal Text><Symbol>(</Symbol><Normal Text>rf_dataw</Normal Text><Symbol>),</Symbol><br/>
1753 <Normal Text> .ce_b</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
1754 <Normal Text> .we_b</Normal Text><Symbol>(</Symbol><Normal Text>tb_enw</Normal Text><Symbol>)</Symbol><br/>
1755 <Symbol>);</Symbol><br/>
1756 <Normal Text></Normal Text><br/>
1757 <Normal Text>or1200_dpram_256x32 tbts_ram</Normal Text><Symbol>(</Symbol><br/>
1758 <Normal Text> .clk_a</Normal Text><Symbol>(</Symbol><Normal Text>clk</Normal Text><Symbol>),</Symbol><br/>
1759 <Normal Text> .rst_a</Normal Text><Symbol>(</Symbol><Binary>1'b0</Binary><Symbol>),</Symbol><br/>
1760 <Normal Text> .addr_a</Normal Text><Symbol>(</Symbol><Normal Text>spr_addr</Normal Text><Symbol>[</Symbol><Integer>7</Integer><Symbol>:</Symbol><Integer>0</Integer><Symbol>]),</Symbol><br/>
1761 <Normal Text> .ce_a</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
1762 <Normal Text> .oe_a</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
1763 <Normal Text> .do_a</Normal Text><Symbol>(</Symbol><Normal Text>tbts_dat_o</Normal Text><Symbol>),</Symbol><br/>
1764 <Normal Text></Normal Text><br/>
1765 <Normal Text> .clk_b</Normal Text><Symbol>(</Symbol><Normal Text>clk</Normal Text><Symbol>),</Symbol><br/>
1766 <Normal Text> .rst_b</Normal Text><Symbol>(</Symbol><Binary>1'b0</Binary><Symbol>),</Symbol><br/>
1767 <Normal Text> .addr_b</Normal Text><Symbol>(</Symbol><Normal Text>tb_wadr</Normal Text><Symbol>),</Symbol><br/>
1768 <Normal Text> .di_b</Normal Text><Symbol>(</Symbol><Normal Text>tb_timstmp</Normal Text><Symbol>),</Symbol><br/>
1769 <Normal Text> .ce_b</Normal Text><Symbol>(</Symbol><Binary>1'b1</Binary><Symbol>),</Symbol><br/>
1770 <Normal Text> .we_b</Normal Text><Symbol>(</Symbol><Normal Text>tb_enw</Normal Text><Symbol>)</Symbol><br/>
1771 <Symbol>);</Symbol><br/>
1772 <Normal Text></Normal Text><br/>
1773 <Preprocessor>`else</Preprocessor><br/>
1774 <Normal Text></Normal Text><br/>
1775 <Keyword>assign</Keyword><Normal Text> tbia_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
1776 <Keyword>assign</Keyword><Normal Text> tbim_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
1777 <Keyword>assign</Keyword><Normal Text> tbar_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
1778 <Keyword>assign</Keyword><Normal Text> tbts_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
1779 <Normal Text></Normal Text><br/>
1780 <Preprocessor>`endif </Preprocessor><Comment>// OR1200_DU_TB_IMPLEMENTED</Comment><br/>
1781 <Normal Text></Normal Text><br/>
1782 <Preprocessor>`else </Preprocessor><Comment>// OR1200_DU_IMPLEMENTED</Comment><br/>
1783 <Normal Text></Normal Text><br/>
1784 <Comment>//</Comment><br/>
1785 <Comment>// When DU is not implemented, drive all outputs as would when DU is disabled</Comment><br/>
1786 <Comment>//</Comment><br/>
1787 <Keyword>assign</Keyword><Normal Text> dbg_bp_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1788 <Keyword>assign</Keyword><Normal Text> du_dsr </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Preprocessor>`OR1200_DU_DSR_WIDTH</Preprocessor><Symbol>{</Symbol><Binary>1'b0</Binary><Symbol>}};</Symbol><br/>
1789 <Keyword>assign</Keyword><Normal Text> du_dmr1 </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Symbol>{</Symbol><Integer>25</Integer><Symbol>{</Symbol><Binary>1'b0</Binary><Symbol>}};</Symbol><br/>
1790 <Keyword>assign</Keyword><Normal Text> du_hwbkpt </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Binary>1'b0</Binary><Symbol>;</Symbol><br/>
1791 <Normal Text></Normal Text><br/>
1792 <Comment>//</Comment><br/>
1793 <Comment>// Read DU registers</Comment><br/>
1794 <Comment>//</Comment><br/>
1795 <Preprocessor>`ifdef OR1200_DU_READREGS</Preprocessor><br/>
1796 <Keyword>assign</Keyword><Normal Text> spr_dat_o </Normal Text><Symbol>=</Symbol><Normal Text> </Normal Text><Hex>32'h0000_0000</Hex><Symbol>;</Symbol><br/>
1797 <Preprocessor>`ifdef OR1200_DU_UNUSED_ZERO</Preprocessor><br/>
1798 <Preprocessor>`endif</Preprocessor><br/>
1799 <Preprocessor>`endif</Preprocessor><br/>
1800 <Normal Text></Normal Text><br/>
1801 <Preprocessor>`endif</Preprocessor><br/>
1802 <Normal Text></Normal Text><br/>
1803 <Keyword>endmodule</Keyword><br/>