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0001 ////////////////////////////////////////////////////////////////////// 0002 //// //// 0003 //// OR1200's Debug Unit //// 0004 //// //// 0005 //// This file is part of the OpenRISC 1200 project //// 0006 //// http://www.opencores.org/project,or1k //// 0007 //// //// 0008 //// Description //// 0009 //// Basic OR1200 debug unit. //// 0010 //// //// 0011 //// To Do: //// 0012 //// - make it smaller and faster //// 0013 //// //// 0014 //// Author(s): //// 0015 //// - Damjan Lampret, lampret@opencores.org //// 0016 //// //// 0017 ////////////////////////////////////////////////////////////////////// 0018 //// //// 0019 //// Copyright (C) 2000 Authors and OPENCORES.ORG //// 0020 //// //// 0021 //// This source file may be used and distributed without //// 0022 //// restriction provided that this copyright statement is not //// 0023 //// removed from the file and that any derivative work contains //// 0024 //// the original copyright notice and the associated disclaimer. //// 0025 //// //// 0026 //// This source file is free software; you can redistribute it //// 0027 //// and/or modify it under the terms of the GNU Lesser General //// 0028 //// Public License as published by the Free Software Foundation; //// 0029 //// either version 2.1 of the License, or (at your option) any //// 0030 //// later version. //// 0031 //// //// 0032 //// This source is distributed in the hope that it will be //// 0033 //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 0034 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 0035 //// PURPOSE. See the GNU Lesser General Public License for more //// 0036 //// details. //// 0037 //// //// 0038 //// You should have received a copy of the GNU Lesser General //// 0039 //// Public License along with this source; if not, download it //// 0040 //// from http://www.opencores.org/lgpl.shtml //// 0041 //// //// 0042 ////////////////////////////////////////////////////////////////////// 0043 // 0044 // 0045 // $Log: or1200_du.v,v $ 0046 // Revision 2.0 2010/06/30 11:00:00 ORSoC 0047 // Minor update: 0048 // Bugs fixed. 0049 0050 // synopsys translate_off 0051 `include "timescale.v" 0052 // synopsys translate_on 0053 `include "or1200_defines.v" 0054 0055 // 0056 // Debug unit 0057 // 0058 0059 module or1200_du( 0060 // RISC Internal Interface 0061 clk, rst, 0062 dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu, 0063 dcpu_dat_dc, icpu_cycstb_i, 0064 ex_freeze, branch_op, ex_insn, id_pc, 0065 spr_dat_npc, rf_dataw, 0066 du_dsr, du_dmr1, du_stall, du_addr, du_dat_i, du_dat_o, 0067 du_read, du_write, du_except_stop, du_hwbkpt, du_flush_pipe, 0068 spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, 0069 0070 // External Debug Interface 0071 dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, 0072 dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o 0073 ); 0074 0075 parameter dw = `OR1200_OPERAND_WIDTH; 0076 parameter aw = `OR1200_OPERAND_WIDTH; 0077 0078 // 0079 // I/O 0080 // 0081 0082 // 0083 // RISC Internal Interface 0084 // 0085 input clk; // Clock 0086 input rst; // Reset 0087 input dcpu_cycstb_i; // LSU status 0088 input dcpu_we_i; // LSU status 0089 input [31:0] dcpu_adr_i; // LSU addr 0090 input [31:0] dcpu_dat_lsu; // LSU store data 0091 input [31:0] dcpu_dat_dc; // LSU load data 0092 input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cycstb_i; // IFETCH unit status 0093 input ex_freeze; // EX stage freeze 0094 input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op 0095 input [dw-1:0] ex_insn; // EX insn 0096 input [31:0] id_pc; // insn fetch EA 0097 input [31:0] spr_dat_npc; // Next PC (for trace) 0098 input [31:0] rf_dataw; // ALU result (for trace) 0099 output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR 0100 output [24: 0] du_dmr1; 0101 output du_stall; // Debug Unit Stall 0102 output [aw-1:0] du_addr; // Debug Unit Address 0103 input [dw-1:0] du_dat_i; // Debug Unit Data In 0104 output [dw-1:0] du_dat_o; // Debug Unit Data Out 0105 output du_read; // Debug Unit Read Enable 0106 output du_write; // Debug Unit Write Enable 0107 input [13:0] du_except_stop; // Exception masked by DSR 0108 output du_hwbkpt; // Cause trap exception (HW Breakpoints) 0109 output du_flush_pipe; // Cause pipeline flush and pc<-npc 0110 input spr_cs; // SPR Chip Select 0111 input spr_write; // SPR Read/Write 0112 input [aw-1:0] spr_addr; // SPR Address 0113 input [dw-1:0] spr_dat_i; // SPR Data Input 0114 output [dw-1:0] spr_dat_o; // SPR Data Output 0115 0116 // 0117 // External Debug Interface 0118 // 0119 input dbg_stall_i; // External Stall Input 0120 input dbg_ewt_i; // External Watchpoint Trigger Input 0121 output [3:0] dbg_lss_o; // External Load/Store Unit Status 0122 output [1:0] dbg_is_o; // External Insn Fetch Status 0123 output [10:0] dbg_wp_o; // Watchpoints Outputs 0124 output dbg_bp_o; // Breakpoint Output 0125 input dbg_stb_i; // External Address/Data Strobe 0126 input dbg_we_i; // External Write Enable 0127 input [aw-1:0] dbg_adr_i; // External Address Input 0128 input [dw-1:0] dbg_dat_i; // External Data Input 0129 output [dw-1:0] dbg_dat_o; // External Data Output 0130 output dbg_ack_o; // External Data Acknowledge (not WB compatible) 0131 reg [dw-1:0] dbg_dat_o; // External Data Output 0132 reg dbg_ack_o; // External Data Acknowledge (not WB compatible) 0133 0134 0135 // 0136 // Some connections go directly from the CPU through DU to Debug I/F 0137 // 0138 `ifdef OR1200_DU_STATUS_UNIMPLEMENTED 0139 assign dbg_lss_o = 4'b0000; 0140 0141 reg [1:0] dbg_is_o; 0142 // 0143 // Show insn activity (temp, must be removed) 0144 // 0145 always @(posedge clk or `OR1200_RST_EVENT rst) 0146 if (rst == `OR1200_RST_VALUE) 0147 dbg_is_o <= 2'b00; 0148 else if (!ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16])) 0149 dbg_is_o <= ~dbg_is_o; 0150 `ifdef UNUSED 0151 assign dbg_is_o = 2'b00; 0152 `endif 0153 `else 0154 assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000; 0155 assign dbg_is_o = {1'b0, icpu_cycstb_i}; 0156 `endif 0157 assign dbg_wp_o = 11'b000_0000_0000; 0158 0159 // 0160 // Some connections go directly from Debug I/F through DU to the CPU 0161 // 0162 assign du_stall = dbg_stall_i; 0163 assign du_addr = dbg_adr_i; 0164 assign du_dat_o = dbg_dat_i; 0165 assign du_read = dbg_stb_i && !dbg_we_i; 0166 assign du_write = dbg_stb_i && dbg_we_i; 0167 0168 // 0169 // After a sw breakpoint, the replaced instruction need to be executed. 0170 // We flush the entire pipeline and set the pc to the current address 0171 // to execute the restored address. 0172 // 0173 0174 reg du_flush_pipe_r; 0175 reg dbg_stall_i_r; 0176 0177 assign du_flush_pipe = du_flush_pipe_r; 0178 0179 // 0180 // Register du_flush_pipe 0181 // 0182 always @(posedge clk or `OR1200_RST_EVENT rst) begin 0183 if (rst == `OR1200_RST_VALUE) begin 0184 du_flush_pipe_r <= 1'b0; 0185 end 0186 else begin 0187 du_flush_pipe_r <= (dbg_stall_i_r && !dbg_stall_i && |du_except_stop); 0188 end 0189 end 0190 0191 // 0192 // Detect dbg_stall falling edge 0193 // 0194 always @(posedge clk or `OR1200_RST_EVENT rst) begin 0195 if (rst == `OR1200_RST_VALUE) begin 0196 dbg_stall_i_r <= 1'b0; 0197 end 0198 else begin 0199 dbg_stall_i_r <= dbg_stall_i; 0200 end 0201 end 0202 0203 reg dbg_ack; 0204 // 0205 // Generate acknowledge -- just delay stb signal 0206 // 0207 always @(posedge clk or `OR1200_RST_EVENT rst) begin 0208 if (rst == `OR1200_RST_VALUE) begin 0209 dbg_ack <= 1'b0; 0210 dbg_ack_o <= 1'b0; 0211 end 0212 else begin 0213 dbg_ack <= dbg_stb_i; // valid when du_dat_i 0214 dbg_ack_o <= dbg_ack & dbg_stb_i; // valid when dbg_dat_o 0215 end 0216 end 0217 0218 // 0219 // Register data output 0220 // 0221 always @(posedge clk) 0222 dbg_dat_o <= du_dat_i; 0223 0224 `ifdef OR1200_DU_IMPLEMENTED 0225 0226 // 0227 // Debug Mode Register 1 0228 // 0229 `ifdef OR1200_DU_DMR1 0230 reg [24:0] dmr1; // DMR1 implemented 0231 `else 0232 wire [24:0] dmr1; // DMR1 not implemented 0233 `endif 0234 assign du_dmr1 = dmr1; 0235 0236 // 0237 // Debug Mode Register 2 0238 // 0239 `ifdef OR1200_DU_DMR2 0240 reg [23:0] dmr2; // DMR2 implemented 0241 `else 0242 wire [23:0] dmr2; // DMR2 not implemented 0243 `endif 0244 0245 // 0246 // Debug Stop Register 0247 // 0248 `ifdef OR1200_DU_DSR 0249 reg [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR implemented 0250 `else 0251 wire [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR not implemented 0252 `endif 0253 0254 // 0255 // Debug Reason Register 0256 // 0257 `ifdef OR1200_DU_DRR 0258 reg [13:0] drr; // DRR implemented 0259 `else 0260 wire [13:0] drr; // DRR not implemented 0261 `endif 0262 0263 // 0264 // Debug Value Register N 0265 // 0266 `ifdef OR1200_DU_DVR0 0267 reg [31:0] dvr0; 0268 `else 0269 wire [31:0] dvr0; 0270 `endif 0271 0272 // 0273 // Debug Value Register N 0274 // 0275 `ifdef OR1200_DU_DVR1 0276 reg [31:0] dvr1; 0277 `else 0278 wire [31:0] dvr1; 0279 `endif 0280 0281 // 0282 // Debug Value Register N 0283 // 0284 `ifdef OR1200_DU_DVR2 0285 reg [31:0] dvr2; 0286 `else 0287 wire [31:0] dvr2; 0288 `endif 0289 0290 // 0291 // Debug Value Register N 0292 // 0293 `ifdef OR1200_DU_DVR3 0294 reg [31:0] dvr3; 0295 `else 0296 wire [31:0] dvr3; 0297 `endif 0298 0299 // 0300 // Debug Value Register N 0301 // 0302 `ifdef OR1200_DU_DVR4 0303 reg [31:0] dvr4; 0304 `else 0305 wire [31:0] dvr4; 0306 `endif 0307 0308 // 0309 // Debug Value Register N 0310 // 0311 `ifdef OR1200_DU_DVR5 0312 reg [31:0] dvr5; 0313 `else 0314 wire [31:0] dvr5; 0315 `endif 0316 0317 // 0318 // Debug Value Register N 0319 // 0320 `ifdef OR1200_DU_DVR6 0321 reg [31:0] dvr6; 0322 `else 0323 wire [31:0] dvr6; 0324 `endif 0325 0326 // 0327 // Debug Value Register N 0328 // 0329 `ifdef OR1200_DU_DVR7 0330 reg [31:0] dvr7; 0331 `else 0332 wire [31:0] dvr7; 0333 `endif 0334 0335 // 0336 // Debug Control Register N 0337 // 0338 `ifdef OR1200_DU_DCR0 0339 reg [7:0] dcr0; 0340 `else 0341 wire [7:0] dcr0; 0342 `endif 0343 0344 // 0345 // Debug Control Register N 0346 // 0347 `ifdef OR1200_DU_DCR1 0348 reg [7:0] dcr1; 0349 `else 0350 wire [7:0] dcr1; 0351 `endif 0352 0353 // 0354 // Debug Control Register N 0355 // 0356 `ifdef OR1200_DU_DCR2 0357 reg [7:0] dcr2; 0358 `else 0359 wire [7:0] dcr2; 0360 `endif 0361 0362 // 0363 // Debug Control Register N 0364 // 0365 `ifdef OR1200_DU_DCR3 0366 reg [7:0] dcr3; 0367 `else 0368 wire [7:0] dcr3; 0369 `endif 0370 0371 // 0372 // Debug Control Register N 0373 // 0374 `ifdef OR1200_DU_DCR4 0375 reg [7:0] dcr4; 0376 `else 0377 wire [7:0] dcr4; 0378 `endif 0379 0380 // 0381 // Debug Control Register N 0382 // 0383 `ifdef OR1200_DU_DCR5 0384 reg [7:0] dcr5; 0385 `else 0386 wire [7:0] dcr5; 0387 `endif 0388 0389 // 0390 // Debug Control Register N 0391 // 0392 `ifdef OR1200_DU_DCR6 0393 reg [7:0] dcr6; 0394 `else 0395 wire [7:0] dcr6; 0396 `endif 0397 0398 // 0399 // Debug Control Register N 0400 // 0401 `ifdef OR1200_DU_DCR7 0402 reg [7:0] dcr7; 0403 `else 0404 wire [7:0] dcr7; 0405 `endif 0406 0407 // 0408 // Debug Watchpoint Counter Register 0 0409 // 0410 `ifdef OR1200_DU_DWCR0 0411 reg [31:0] dwcr0; 0412 `else 0413 wire [31:0] dwcr0; 0414 `endif 0415 0416 // 0417 // Debug Watchpoint Counter Register 1 0418 // 0419 `ifdef OR1200_DU_DWCR1 0420 reg [31:0] dwcr1; 0421 `else 0422 wire [31:0] dwcr1; 0423 `endif 0424 0425 // 0426 // Internal wires 0427 // 0428 wire dmr1_sel; // DMR1 select 0429 wire dmr2_sel; // DMR2 select 0430 wire dsr_sel; // DSR select 0431 wire drr_sel; // DRR select 0432 wire dvr0_sel, 0433 dvr1_sel, 0434 dvr2_sel, 0435 dvr3_sel, 0436 dvr4_sel, 0437 dvr5_sel, 0438 dvr6_sel, 0439 dvr7_sel; // DVR selects 0440 wire dcr0_sel, 0441 dcr1_sel, 0442 dcr2_sel, 0443 dcr3_sel, 0444 dcr4_sel, 0445 dcr5_sel, 0446 dcr6_sel, 0447 dcr7_sel; // DCR selects 0448 wire dwcr0_sel, 0449 dwcr1_sel; // DWCR selects 0450 reg dbg_bp_r; 0451 reg ex_freeze_q; 0452 `ifdef OR1200_DU_HWBKPTS 0453 reg [31:0] match_cond0_ct; 0454 reg [31:0] match_cond1_ct; 0455 reg [31:0] match_cond2_ct; 0456 reg [31:0] match_cond3_ct; 0457 reg [31:0] match_cond4_ct; 0458 reg [31:0] match_cond5_ct; 0459 reg [31:0] match_cond6_ct; 0460 reg [31:0] match_cond7_ct; 0461 reg match_cond0_stb; 0462 reg match_cond1_stb; 0463 reg match_cond2_stb; 0464 reg match_cond3_stb; 0465 reg match_cond4_stb; 0466 reg match_cond5_stb; 0467 reg match_cond6_stb; 0468 reg match_cond7_stb; 0469 reg match0; 0470 reg match1; 0471 reg match2; 0472 reg match3; 0473 reg match4; 0474 reg match5; 0475 reg match6; 0476 reg match7; 0477 reg wpcntr0_match; 0478 reg wpcntr1_match; 0479 reg incr_wpcntr0; 0480 reg incr_wpcntr1; 0481 reg [10:0] wp; 0482 `endif 0483 wire du_hwbkpt; 0484 reg du_hwbkpt_hold; 0485 `ifdef OR1200_DU_READREGS 0486 reg [31:0] spr_dat_o; 0487 `endif 0488 reg [13:0] except_stop; // Exceptions that stop because of DSR 0489 `ifdef OR1200_DU_TB_IMPLEMENTED 0490 wire tb_enw; 0491 reg [7:0] tb_wadr; 0492 reg [31:0] tb_timstmp; 0493 `endif 0494 wire [31:0] tbia_dat_o; 0495 wire [31:0] tbim_dat_o; 0496 wire [31:0] tbar_dat_o; 0497 wire [31:0] tbts_dat_o; 0498 0499 // 0500 // DU registers address decoder 0501 // 0502 `ifdef OR1200_DU_DMR1 0503 assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR1)); 0504 `endif 0505 `ifdef OR1200_DU_DMR2 0506 assign dmr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR2)); 0507 `endif 0508 `ifdef OR1200_DU_DSR 0509 assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DSR)); 0510 `endif 0511 `ifdef OR1200_DU_DRR 0512 assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DRR)); 0513 `endif 0514 `ifdef OR1200_DU_DVR0 0515 assign dvr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR0)); 0516 `endif 0517 `ifdef OR1200_DU_DVR1 0518 assign dvr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR1)); 0519 `endif 0520 `ifdef OR1200_DU_DVR2 0521 assign dvr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR2)); 0522 `endif 0523 `ifdef OR1200_DU_DVR3 0524 assign dvr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR3)); 0525 `endif 0526 `ifdef OR1200_DU_DVR4 0527 assign dvr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR4)); 0528 `endif 0529 `ifdef OR1200_DU_DVR5 0530 assign dvr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR5)); 0531 `endif 0532 `ifdef OR1200_DU_DVR6 0533 assign dvr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR6)); 0534 `endif 0535 `ifdef OR1200_DU_DVR7 0536 assign dvr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR7)); 0537 `endif 0538 `ifdef OR1200_DU_DCR0 0539 assign dcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR0)); 0540 `endif 0541 `ifdef OR1200_DU_DCR1 0542 assign dcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR1)); 0543 `endif 0544 `ifdef OR1200_DU_DCR2 0545 assign dcr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR2)); 0546 `endif 0547 `ifdef OR1200_DU_DCR3 0548 assign dcr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR3)); 0549 `endif 0550 `ifdef OR1200_DU_DCR4 0551 assign dcr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR4)); 0552 `endif 0553 `ifdef OR1200_DU_DCR5 0554 assign dcr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR5)); 0555 `endif 0556 `ifdef OR1200_DU_DCR6 0557 assign dcr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR6)); 0558 `endif 0559 `ifdef OR1200_DU_DCR7 0560 assign dcr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR7)); 0561 `endif 0562 `ifdef OR1200_DU_DWCR0 0563 assign dwcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR0)); 0564 `endif 0565 `ifdef OR1200_DU_DWCR1 0566 assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1)); 0567 `endif 0568 0569 // Track previous ex_freeze to detect when signals are updated 0570 always @(posedge clk) 0571 ex_freeze_q <= ex_freeze; 0572 0573 // 0574 // Decode started exception 0575 // 0576 // du_except_stop comes from or1200_except 0577 // 0578 always @(du_except_stop or ex_freeze_q) begin 0579 except_stop = 14'b00_0000_0000_0000; 0580 casez (du_except_stop) 0581 14'b1?_????_????_????: 0582 except_stop[`OR1200_DU_DRR_TTE] = 1'b1; 0583 14'b01_????_????_????: begin 0584 except_stop[`OR1200_DU_DRR_IE] = 1'b1; 0585 end 0586 14'b00_1???_????_????: begin 0587 except_stop[`OR1200_DU_DRR_IME] = 1'b1; 0588 end 0589 14'b00_01??_????_????: 0590 except_stop[`OR1200_DU_DRR_IPFE] = 1'b1; 0591 14'b00_001?_????_????: begin 0592 except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1; 0593 end 0594 14'b00_0001_????_????: 0595 except_stop[`OR1200_DU_DRR_IIE] = 1'b1; 0596 14'b00_0000_1???_????: begin 0597 except_stop[`OR1200_DU_DRR_AE] = 1'b1; 0598 end 0599 14'b00_0000_01??_????: begin 0600 except_stop[`OR1200_DU_DRR_DME] = 1'b1; 0601 end 0602 14'b00_0000_001?_????: 0603 except_stop[`OR1200_DU_DRR_DPFE] = 1'b1; 0604 14'b00_0000_0001_????: 0605 except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1; 0606 14'b00_0000_0000_1???: begin 0607 except_stop[`OR1200_DU_DRR_RE] = 1'b1; 0608 end 0609 14'b00_0000_0000_01??: begin 0610 except_stop[`OR1200_DU_DRR_TE] = 1'b1 & ~ex_freeze_q; 0611 end 0612 14'b00_0000_0000_001?: begin 0613 except_stop[`OR1200_DU_DRR_FPE] = 1'b1; 0614 end 0615 14'b00_0000_0000_0001: 0616 except_stop[`OR1200_DU_DRR_SCE] = 1'b1 & ~ex_freeze_q; 0617 default: 0618 except_stop = 14'b00_0000_0000_0000; 0619 endcase // casez (du_except_stop) 0620 end 0621 0622 // 0623 // dbg_bp_o is registered 0624 // 0625 assign dbg_bp_o = dbg_bp_r; 0626 0627 // 0628 // Breakpoint activation register 0629 // 0630 always @(posedge clk or `OR1200_RST_EVENT rst) 0631 if (rst == `OR1200_RST_VALUE) 0632 dbg_bp_r <= 1'b0; 0633 else if (!ex_freeze) 0634 dbg_bp_r <= |except_stop 0635 `ifdef OR1200_DU_DMR1_ST 0636 | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST] 0637 `endif 0638 `ifdef OR1200_DU_DMR1_BT 0639 | (branch_op != `OR1200_BRANCHOP_NOP) & (branch_op != `OR1200_BRANCHOP_RFE) & dmr1[`OR1200_DU_DMR1_BT] 0640 `endif 0641 ; 0642 else 0643 dbg_bp_r <= |except_stop; 0644 0645 // 0646 // Write to DMR1 0647 // 0648 `ifdef OR1200_DU_DMR1 0649 always @(posedge clk or `OR1200_RST_EVENT rst) 0650 if (rst == `OR1200_RST_VALUE) 0651 dmr1 <= 25'h000_0000; 0652 else if (dmr1_sel && spr_write) 0653 `ifdef OR1200_DU_HWBKPTS 0654 dmr1 <= spr_dat_i[24:0]; 0655 `else 0656 dmr1 <= {1'b0, spr_dat_i[23:22], 22'h00_0000}; 0657 `endif 0658 `else 0659 assign dmr1 = 25'h000_0000; 0660 `endif 0661 0662 // 0663 // Write to DMR2 0664 // 0665 `ifdef OR1200_DU_DMR2 0666 always @(posedge clk or `OR1200_RST_EVENT rst) 0667 if (rst == `OR1200_RST_VALUE) 0668 dmr2 <= 24'h00_0000; 0669 else if (dmr2_sel && spr_write) 0670 dmr2 <= spr_dat_i[23:0]; 0671 `else 0672 assign dmr2 = 24'h00_0000; 0673 `endif 0674 0675 // 0676 // Write to DSR 0677 // 0678 `ifdef OR1200_DU_DSR 0679 always @(posedge clk or `OR1200_RST_EVENT rst) 0680 if (rst == `OR1200_RST_VALUE) 0681 dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}}; 0682 else if (dsr_sel && spr_write) 0683 dsr <= spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0]; 0684 `else 0685 assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}}; 0686 `endif 0687 0688 // 0689 // Write to DRR 0690 // 0691 `ifdef OR1200_DU_DRR 0692 always @(posedge clk or `OR1200_RST_EVENT rst) 0693 if (rst == `OR1200_RST_VALUE) 0694 drr <= 14'b0; 0695 else if (drr_sel && spr_write) 0696 drr <= spr_dat_i[13:0]; 0697 else 0698 drr <= drr | except_stop; 0699 `else 0700 assign drr = 14'b0; 0701 `endif 0702 0703 // 0704 // Write to DVR0 0705 // 0706 `ifdef OR1200_DU_DVR0 0707 always @(posedge clk or `OR1200_RST_EVENT rst) 0708 if (rst == `OR1200_RST_VALUE) 0709 dvr0 <= 32'h0000_0000; 0710 else if (dvr0_sel && spr_write) 0711 dvr0 <= spr_dat_i[31:0]; 0712 `else 0713 assign dvr0 = 32'h0000_0000; 0714 `endif 0715 0716 // 0717 // Write to DVR1 0718 // 0719 `ifdef OR1200_DU_DVR1 0720 always @(posedge clk or `OR1200_RST_EVENT rst) 0721 if (rst == `OR1200_RST_VALUE) 0722 dvr1 <= 32'h0000_0000; 0723 else if (dvr1_sel && spr_write) 0724 dvr1 <= spr_dat_i[31:0]; 0725 `else 0726 assign dvr1 = 32'h0000_0000; 0727 `endif 0728 0729 // 0730 // Write to DVR2 0731 // 0732 `ifdef OR1200_DU_DVR2 0733 always @(posedge clk or `OR1200_RST_EVENT rst) 0734 if (rst == `OR1200_RST_VALUE) 0735 dvr2 <= 32'h0000_0000; 0736 else if (dvr2_sel && spr_write) 0737 dvr2 <= spr_dat_i[31:0]; 0738 `else 0739 assign dvr2 = 32'h0000_0000; 0740 `endif 0741 0742 // 0743 // Write to DVR3 0744 // 0745 `ifdef OR1200_DU_DVR3 0746 always @(posedge clk or `OR1200_RST_EVENT rst) 0747 if (rst == `OR1200_RST_VALUE) 0748 dvr3 <= 32'h0000_0000; 0749 else if (dvr3_sel && spr_write) 0750 dvr3 <= spr_dat_i[31:0]; 0751 `else 0752 assign dvr3 = 32'h0000_0000; 0753 `endif 0754 0755 // 0756 // Write to DVR4 0757 // 0758 `ifdef OR1200_DU_DVR4 0759 always @(posedge clk or `OR1200_RST_EVENT rst) 0760 if (rst == `OR1200_RST_VALUE) 0761 dvr4 <= 32'h0000_0000; 0762 else if (dvr4_sel && spr_write) 0763 dvr4 <= spr_dat_i[31:0]; 0764 `else 0765 assign dvr4 = 32'h0000_0000; 0766 `endif 0767 0768 // 0769 // Write to DVR5 0770 // 0771 `ifdef OR1200_DU_DVR5 0772 always @(posedge clk or `OR1200_RST_EVENT rst) 0773 if (rst == `OR1200_RST_VALUE) 0774 dvr5 <= 32'h0000_0000; 0775 else if (dvr5_sel && spr_write) 0776 dvr5 <= spr_dat_i[31:0]; 0777 `else 0778 assign dvr5 = 32'h0000_0000; 0779 `endif 0780 0781 // 0782 // Write to DVR6 0783 // 0784 `ifdef OR1200_DU_DVR6 0785 always @(posedge clk or `OR1200_RST_EVENT rst) 0786 if (rst == `OR1200_RST_VALUE) 0787 dvr6 <= 32'h0000_0000; 0788 else if (dvr6_sel && spr_write) 0789 dvr6 <= spr_dat_i[31:0]; 0790 `else 0791 assign dvr6 = 32'h0000_0000; 0792 `endif 0793 0794 // 0795 // Write to DVR7 0796 // 0797 `ifdef OR1200_DU_DVR7 0798 always @(posedge clk or `OR1200_RST_EVENT rst) 0799 if (rst == `OR1200_RST_VALUE) 0800 dvr7 <= 32'h0000_0000; 0801 else if (dvr7_sel && spr_write) 0802 dvr7 <= spr_dat_i[31:0]; 0803 `else 0804 assign dvr7 = 32'h0000_0000; 0805 `endif 0806 0807 // 0808 // Write to DCR0 0809 // 0810 `ifdef OR1200_DU_DCR0 0811 always @(posedge clk or `OR1200_RST_EVENT rst) 0812 if (rst == `OR1200_RST_VALUE) 0813 dcr0 <= 8'h00; 0814 else if (dcr0_sel && spr_write) 0815 dcr0 <= spr_dat_i[7:0]; 0816 `else 0817 assign dcr0 = 8'h00; 0818 `endif 0819 0820 // 0821 // Write to DCR1 0822 // 0823 `ifdef OR1200_DU_DCR1 0824 always @(posedge clk or `OR1200_RST_EVENT rst) 0825 if (rst == `OR1200_RST_VALUE) 0826 dcr1 <= 8'h00; 0827 else if (dcr1_sel && spr_write) 0828 dcr1 <= spr_dat_i[7:0]; 0829 `else 0830 assign dcr1 = 8'h00; 0831 `endif 0832 0833 // 0834 // Write to DCR2 0835 // 0836 `ifdef OR1200_DU_DCR2 0837 always @(posedge clk or `OR1200_RST_EVENT rst) 0838 if (rst == `OR1200_RST_VALUE) 0839 dcr2 <= 8'h00; 0840 else if (dcr2_sel && spr_write) 0841 dcr2 <= spr_dat_i[7:0]; 0842 `else 0843 assign dcr2 = 8'h00; 0844 `endif 0845 0846 // 0847 // Write to DCR3 0848 // 0849 `ifdef OR1200_DU_DCR3 0850 always @(posedge clk or `OR1200_RST_EVENT rst) 0851 if (rst == `OR1200_RST_VALUE) 0852 dcr3 <= 8'h00; 0853 else if (dcr3_sel && spr_write) 0854 dcr3 <= spr_dat_i[7:0]; 0855 `else 0856 assign dcr3 = 8'h00; 0857 `endif 0858 0859 // 0860 // Write to DCR4 0861 // 0862 `ifdef OR1200_DU_DCR4 0863 always @(posedge clk or `OR1200_RST_EVENT rst) 0864 if (rst == `OR1200_RST_VALUE) 0865 dcr4 <= 8'h00; 0866 else if (dcr4_sel && spr_write) 0867 dcr4 <= spr_dat_i[7:0]; 0868 `else 0869 assign dcr4 = 8'h00; 0870 `endif 0871 0872 // 0873 // Write to DCR5 0874 // 0875 `ifdef OR1200_DU_DCR5 0876 always @(posedge clk or `OR1200_RST_EVENT rst) 0877 if (rst == `OR1200_RST_VALUE) 0878 dcr5 <= 8'h00; 0879 else if (dcr5_sel && spr_write) 0880 dcr5 <= spr_dat_i[7:0]; 0881 `else 0882 assign dcr5 = 8'h00; 0883 `endif 0884 0885 // 0886 // Write to DCR6 0887 // 0888 `ifdef OR1200_DU_DCR6 0889 always @(posedge clk or `OR1200_RST_EVENT rst) 0890 if (rst == `OR1200_RST_VALUE) 0891 dcr6 <= 8'h00; 0892 else if (dcr6_sel && spr_write) 0893 dcr6 <= spr_dat_i[7:0]; 0894 `else 0895 assign dcr6 = 8'h00; 0896 `endif 0897 0898 // 0899 // Write to DCR7 0900 // 0901 `ifdef OR1200_DU_DCR7 0902 always @(posedge clk or `OR1200_RST_EVENT rst) 0903 if (rst == `OR1200_RST_VALUE) 0904 dcr7 <= 8'h00; 0905 else if (dcr7_sel && spr_write) 0906 dcr7 <= spr_dat_i[7:0]; 0907 `else 0908 assign dcr7 = 8'h00; 0909 `endif 0910 0911 // 0912 // Write to DWCR0 0913 // 0914 `ifdef OR1200_DU_DWCR0 0915 always @(posedge clk or `OR1200_RST_EVENT rst) 0916 if (rst == `OR1200_RST_VALUE) 0917 dwcr0 <= 32'h0000_0000; 0918 else if (dwcr0_sel && spr_write) 0919 dwcr0 <= spr_dat_i[31:0]; 0920 else if (incr_wpcntr0) 0921 dwcr0[`OR1200_DU_DWCR_COUNT] <= dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001; 0922 `else 0923 assign dwcr0 = 32'h0000_0000; 0924 `endif 0925 0926 // 0927 // Write to DWCR1 0928 // 0929 `ifdef OR1200_DU_DWCR1 0930 always @(posedge clk or `OR1200_RST_EVENT rst) 0931 if (rst == `OR1200_RST_VALUE) 0932 dwcr1 <= 32'h0000_0000; 0933 else if (dwcr1_sel && spr_write) 0934 dwcr1 <= spr_dat_i[31:0]; 0935 else if (incr_wpcntr1) 0936 dwcr1[`OR1200_DU_DWCR_COUNT] <= dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001; 0937 `else 0938 assign dwcr1 = 32'h0000_0000; 0939 `endif 0940 0941 // 0942 // Read DU registers 0943 // 0944 `ifdef OR1200_DU_READREGS 0945 always @(spr_addr or dsr or drr or dmr1 or dmr2 0946 or dvr0 or dvr1 or dvr2 or dvr3 or dvr4 0947 or dvr5 or dvr6 or dvr7 0948 or dcr0 or dcr1 or dcr2 or dcr3 or dcr4 0949 or dcr5 or dcr6 or dcr7 0950 or dwcr0 or dwcr1 0951 `ifdef OR1200_DU_TB_IMPLEMENTED 0952 or tb_wadr or tbia_dat_o or tbim_dat_o 0953 or tbar_dat_o or tbts_dat_o 0954 `endif 0955 ) 0956 casez (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case 0957 `ifdef OR1200_DU_DVR0 0958 `OR1200_DU_DVR0: 0959 spr_dat_o = dvr0; 0960 `endif 0961 `ifdef OR1200_DU_DVR1 0962 `OR1200_DU_DVR1: 0963 spr_dat_o = dvr1; 0964 `endif 0965 `ifdef OR1200_DU_DVR2 0966 `OR1200_DU_DVR2: 0967 spr_dat_o = dvr2; 0968 `endif 0969 `ifdef OR1200_DU_DVR3 0970 `OR1200_DU_DVR3: 0971 spr_dat_o = dvr3; 0972 `endif 0973 `ifdef OR1200_DU_DVR4 0974 `OR1200_DU_DVR4: 0975 spr_dat_o = dvr4; 0976 `endif 0977 `ifdef OR1200_DU_DVR5 0978 `OR1200_DU_DVR5: 0979 spr_dat_o = dvr5; 0980 `endif 0981 `ifdef OR1200_DU_DVR6 0982 `OR1200_DU_DVR6: 0983 spr_dat_o = dvr6; 0984 `endif 0985 `ifdef OR1200_DU_DVR7 0986 `OR1200_DU_DVR7: 0987 spr_dat_o = dvr7; 0988 `endif 0989 `ifdef OR1200_DU_DCR0 0990 `OR1200_DU_DCR0: 0991 spr_dat_o = {24'h00_0000, dcr0}; 0992 `endif 0993 `ifdef OR1200_DU_DCR1 0994 `OR1200_DU_DCR1: 0995 spr_dat_o = {24'h00_0000, dcr1}; 0996 `endif 0997 `ifdef OR1200_DU_DCR2 0998 `OR1200_DU_DCR2: 0999 spr_dat_o = {24'h00_0000, dcr2}; 1000 `endif 1001 `ifdef OR1200_DU_DCR3 1002 `OR1200_DU_DCR3: 1003 spr_dat_o = {24'h00_0000, dcr3}; 1004 `endif 1005 `ifdef OR1200_DU_DCR4 1006 `OR1200_DU_DCR4: 1007 spr_dat_o = {24'h00_0000, dcr4}; 1008 `endif 1009 `ifdef OR1200_DU_DCR5 1010 `OR1200_DU_DCR5: 1011 spr_dat_o = {24'h00_0000, dcr5}; 1012 `endif 1013 `ifdef OR1200_DU_DCR6 1014 `OR1200_DU_DCR6: 1015 spr_dat_o = {24'h00_0000, dcr6}; 1016 `endif 1017 `ifdef OR1200_DU_DCR7 1018 `OR1200_DU_DCR7: 1019 spr_dat_o = {24'h00_0000, dcr7}; 1020 `endif 1021 `ifdef OR1200_DU_DMR1 1022 `OR1200_DU_DMR1: 1023 spr_dat_o = {7'h00, dmr1}; 1024 `endif 1025 `ifdef OR1200_DU_DMR2 1026 `OR1200_DU_DMR2: 1027 spr_dat_o = {8'h00, dmr2}; 1028 `endif 1029 `ifdef OR1200_DU_DWCR0 1030 `OR1200_DU_DWCR0: 1031 spr_dat_o = dwcr0; 1032 `endif 1033 `ifdef OR1200_DU_DWCR1 1034 `OR1200_DU_DWCR1: 1035 spr_dat_o = dwcr1; 1036 `endif 1037 `ifdef OR1200_DU_DSR 1038 `OR1200_DU_DSR: 1039 spr_dat_o = {18'b0, dsr}; 1040 `endif 1041 `ifdef OR1200_DU_DRR 1042 `OR1200_DU_DRR: 1043 spr_dat_o = {18'b0, drr}; 1044 `endif 1045 `ifdef OR1200_DU_TB_IMPLEMENTED 1046 `OR1200_DU_TBADR: 1047 spr_dat_o = {24'h000000, tb_wadr}; 1048 `OR1200_DU_TBIA: 1049 spr_dat_o = tbia_dat_o; 1050 `OR1200_DU_TBIM: 1051 spr_dat_o = tbim_dat_o; 1052 `OR1200_DU_TBAR: 1053 spr_dat_o = tbar_dat_o; 1054 `OR1200_DU_TBTS: 1055 spr_dat_o = tbts_dat_o; 1056 `endif 1057 default: 1058 spr_dat_o = 32'h0000_0000; 1059 endcase 1060 `endif 1061 1062 // 1063 // DSR alias 1064 // 1065 assign du_dsr = dsr; 1066 1067 `ifdef OR1200_DU_HWBKPTS 1068 1069 // 1070 // Compare To What (Match Condition 0) 1071 // 1072 always @(dcr0 or id_pc or dcpu_adr_i or dcpu_dat_dc 1073 or dcpu_dat_lsu or dcpu_we_i) 1074 case (dcr0[`OR1200_DU_DCR_CT]) // synopsys parallel_case 1075 3'b001: match_cond0_ct = id_pc; // insn fetch EA 1076 3'b010: match_cond0_ct = dcpu_adr_i; // load EA 1077 3'b011: match_cond0_ct = dcpu_adr_i; // store EA 1078 3'b100: match_cond0_ct = dcpu_dat_dc; // load data 1079 3'b101: match_cond0_ct = dcpu_dat_lsu; // store data 1080 3'b110: match_cond0_ct = dcpu_adr_i; // load/store EA 1081 default:match_cond0_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; 1082 endcase 1083 1084 // 1085 // When To Compare (Match Condition 0) 1086 // 1087 always @(dcr0 or dcpu_cycstb_i) 1088 case (dcr0[`OR1200_DU_DCR_CT]) // synopsys parallel_case 1089 3'b000: match_cond0_stb = 1'b0; //comparison disabled 1090 3'b001: match_cond0_stb = 1'b1; // insn fetch EA 1091 default:match_cond0_stb = dcpu_cycstb_i; // any load/store 1092 endcase 1093 1094 // 1095 // Match Condition 0 1096 // 1097 always @(match_cond0_stb or dcr0 or dvr0 or match_cond0_ct) 1098 casex ({match_cond0_stb, dcr0[`OR1200_DU_DCR_CC]}) 1099 4'b0_xxx, 1100 4'b1_000, 1101 4'b1_111: match0 = 1'b0; 1102 4'b1_001: match0 = 1103 ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} == 1104 {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]}); 1105 4'b1_010: match0 = 1106 ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} < 1107 {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]}); 1108 4'b1_011: match0 = 1109 ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <= 1110 {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]}); 1111 4'b1_100: match0 = 1112 ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} > 1113 {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]}); 1114 4'b1_101: match0 = 1115 ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >= 1116 {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]}); 1117 4'b1_110: match0 = 1118 ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} != 1119 {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]}); 1120 endcase 1121 1122 // 1123 // Watchpoint 0 1124 // 1125 always @(dmr1 or match0) 1126 case (dmr1[`OR1200_DU_DMR1_CW0]) 1127 2'b00: wp[0] = match0; 1128 2'b01: wp[0] = match0; 1129 2'b10: wp[0] = match0; 1130 2'b11: wp[0] = 1'b0; 1131 endcase 1132 1133 // 1134 // Compare To What (Match Condition 1) 1135 // 1136 always @(dcr1 or id_pc or dcpu_adr_i or dcpu_dat_dc 1137 or dcpu_dat_lsu or dcpu_we_i) 1138 case (dcr1[`OR1200_DU_DCR_CT]) // synopsys parallel_case 1139 3'b001: match_cond1_ct = id_pc; // insn fetch EA 1140 3'b010: match_cond1_ct = dcpu_adr_i; // load EA 1141 3'b011: match_cond1_ct = dcpu_adr_i; // store EA 1142 3'b100: match_cond1_ct = dcpu_dat_dc; // load data 1143 3'b101: match_cond1_ct = dcpu_dat_lsu; // store data 1144 3'b110: match_cond1_ct = dcpu_adr_i; // load/store EA 1145 default:match_cond1_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; 1146 endcase 1147 1148 // 1149 // When To Compare (Match Condition 1) 1150 // 1151 always @(dcr1 or dcpu_cycstb_i) 1152 case (dcr1[`OR1200_DU_DCR_CT]) // synopsys parallel_case 1153 3'b000: match_cond1_stb = 1'b0; //comparison disabled 1154 3'b001: match_cond1_stb = 1'b1; // insn fetch EA 1155 default:match_cond1_stb = dcpu_cycstb_i; // any load/store 1156 endcase 1157 1158 // 1159 // Match Condition 1 1160 // 1161 always @(match_cond1_stb or dcr1 or dvr1 or match_cond1_ct) 1162 casex ({match_cond1_stb, dcr1[`OR1200_DU_DCR_CC]}) 1163 4'b0_xxx, 1164 4'b1_000, 1165 4'b1_111: match1 = 1'b0; 1166 4'b1_001: match1 = 1167 ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} == 1168 {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]}); 1169 4'b1_010: match1 = 1170 ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} < 1171 {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]}); 1172 4'b1_011: match1 = 1173 ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <= 1174 {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]}); 1175 4'b1_100: match1 = 1176 ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} > 1177 {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]}); 1178 4'b1_101: match1 = 1179 ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >= 1180 {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]}); 1181 4'b1_110: match1 = 1182 ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} != 1183 {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]}); 1184 endcase 1185 1186 // 1187 // Watchpoint 1 1188 // 1189 always @(dmr1 or match1 or wp) 1190 case (dmr1[`OR1200_DU_DMR1_CW1]) 1191 2'b00: wp[1] = match1; 1192 2'b01: wp[1] = match1 & wp[0]; 1193 2'b10: wp[1] = match1 | wp[0]; 1194 2'b11: wp[1] = 1'b0; 1195 endcase 1196 1197 // 1198 // Compare To What (Match Condition 2) 1199 // 1200 always @(dcr2 or id_pc or dcpu_adr_i or dcpu_dat_dc 1201 or dcpu_dat_lsu or dcpu_we_i) 1202 case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case 1203 3'b001: match_cond2_ct = id_pc; // insn fetch EA 1204 3'b010: match_cond2_ct = dcpu_adr_i; // load EA 1205 3'b011: match_cond2_ct = dcpu_adr_i; // store EA 1206 3'b100: match_cond2_ct = dcpu_dat_dc; // load data 1207 3'b101: match_cond2_ct = dcpu_dat_lsu; // store data 1208 3'b110: match_cond2_ct = dcpu_adr_i; // load/store EA 1209 default:match_cond2_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; 1210 endcase 1211 1212 // 1213 // When To Compare (Match Condition 2) 1214 // 1215 always @(dcr2 or dcpu_cycstb_i) 1216 case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case 1217 3'b000: match_cond2_stb = 1'b0; //comparison disabled 1218 3'b001: match_cond2_stb = 1'b1; // insn fetch EA 1219 default:match_cond2_stb = dcpu_cycstb_i; // any load/store 1220 endcase 1221 1222 // 1223 // Match Condition 2 1224 // 1225 always @(match_cond2_stb or dcr2 or dvr2 or match_cond2_ct) 1226 casex ({match_cond2_stb, dcr2[`OR1200_DU_DCR_CC]}) 1227 4'b0_xxx, 1228 4'b1_000, 1229 4'b1_111: match2 = 1'b0; 1230 4'b1_001: match2 = 1231 ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} == 1232 {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]}); 1233 4'b1_010: match2 = 1234 ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} < 1235 {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]}); 1236 4'b1_011: match2 = 1237 ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <= 1238 {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]}); 1239 4'b1_100: match2 = 1240 ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} > 1241 {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]}); 1242 4'b1_101: match2 = 1243 ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >= 1244 {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]}); 1245 4'b1_110: match2 = 1246 ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} != 1247 {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]}); 1248 endcase 1249 1250 // 1251 // Watchpoint 2 1252 // 1253 always @(dmr1 or match2 or wp) 1254 case (dmr1[`OR1200_DU_DMR1_CW2]) 1255 2'b00: wp[2] = match2; 1256 2'b01: wp[2] = match2 & wp[1]; 1257 2'b10: wp[2] = match2 | wp[1]; 1258 2'b11: wp[2] = 1'b0; 1259 endcase 1260 1261 // 1262 // Compare To What (Match Condition 3) 1263 // 1264 always @(dcr3 or id_pc or dcpu_adr_i or dcpu_dat_dc 1265 or dcpu_dat_lsu or dcpu_we_i) 1266 case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case 1267 3'b001: match_cond3_ct = id_pc; // insn fetch EA 1268 3'b010: match_cond3_ct = dcpu_adr_i; // load EA 1269 3'b011: match_cond3_ct = dcpu_adr_i; // store EA 1270 3'b100: match_cond3_ct = dcpu_dat_dc; // load data 1271 3'b101: match_cond3_ct = dcpu_dat_lsu; // store data 1272 3'b110: match_cond3_ct = dcpu_adr_i; // load/store EA 1273 default:match_cond3_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; 1274 endcase 1275 1276 // 1277 // When To Compare (Match Condition 3) 1278 // 1279 always @(dcr3 or dcpu_cycstb_i) 1280 case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case 1281 3'b000: match_cond3_stb = 1'b0; //comparison disabled 1282 3'b001: match_cond3_stb = 1'b1; // insn fetch EA 1283 default:match_cond3_stb = dcpu_cycstb_i; // any load/store 1284 endcase 1285 1286 // 1287 // Match Condition 3 1288 // 1289 always @(match_cond3_stb or dcr3 or dvr3 or match_cond3_ct) 1290 casex ({match_cond3_stb, dcr3[`OR1200_DU_DCR_CC]}) 1291 4'b0_xxx, 1292 4'b1_000, 1293 4'b1_111: match3 = 1'b0; 1294 4'b1_001: match3 = 1295 ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} == 1296 {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]}); 1297 4'b1_010: match3 = 1298 ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} < 1299 {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]}); 1300 4'b1_011: match3 = 1301 ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <= 1302 {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]}); 1303 4'b1_100: match3 = 1304 ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} > 1305 {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]}); 1306 4'b1_101: match3 = 1307 ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >= 1308 {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]}); 1309 4'b1_110: match3 = 1310 ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} != 1311 {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]}); 1312 endcase 1313 1314 // 1315 // Watchpoint 3 1316 // 1317 always @(dmr1 or match3 or wp) 1318 case (dmr1[`OR1200_DU_DMR1_CW3]) 1319 2'b00: wp[3] = match3; 1320 2'b01: wp[3] = match3 & wp[2]; 1321 2'b10: wp[3] = match3 | wp[2]; 1322 2'b11: wp[3] = 1'b0; 1323 endcase 1324 1325 // 1326 // Compare To What (Match Condition 4) 1327 // 1328 always @(dcr4 or id_pc or dcpu_adr_i or dcpu_dat_dc 1329 or dcpu_dat_lsu or dcpu_we_i) 1330 case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case 1331 3'b001: match_cond4_ct = id_pc; // insn fetch EA 1332 3'b010: match_cond4_ct = dcpu_adr_i; // load EA 1333 3'b011: match_cond4_ct = dcpu_adr_i; // store EA 1334 3'b100: match_cond4_ct = dcpu_dat_dc; // load data 1335 3'b101: match_cond4_ct = dcpu_dat_lsu; // store data 1336 3'b110: match_cond4_ct = dcpu_adr_i; // load/store EA 1337 default:match_cond4_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; 1338 endcase 1339 1340 // 1341 // When To Compare (Match Condition 4) 1342 // 1343 always @(dcr4 or dcpu_cycstb_i) 1344 case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case 1345 3'b000: match_cond4_stb = 1'b0; //comparison disabled 1346 3'b001: match_cond4_stb = 1'b1; // insn fetch EA 1347 default:match_cond4_stb = dcpu_cycstb_i; // any load/store 1348 endcase 1349 1350 // 1351 // Match Condition 4 1352 // 1353 always @(match_cond4_stb or dcr4 or dvr4 or match_cond4_ct) 1354 casex ({match_cond4_stb, dcr4[`OR1200_DU_DCR_CC]}) 1355 4'b0_xxx, 1356 4'b1_000, 1357 4'b1_111: match4 = 1'b0; 1358 4'b1_001: match4 = 1359 ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} == 1360 {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]}); 1361 4'b1_010: match4 = 1362 ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} < 1363 {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]}); 1364 4'b1_011: match4 = 1365 ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <= 1366 {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]}); 1367 4'b1_100: match4 = 1368 ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} > 1369 {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]}); 1370 4'b1_101: match4 = 1371 ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >= 1372 {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]}); 1373 4'b1_110: match4 = 1374 ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} != 1375 {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]}); 1376 endcase 1377 1378 // 1379 // Watchpoint 4 1380 // 1381 always @(dmr1 or match4 or wp) 1382 case (dmr1[`OR1200_DU_DMR1_CW4]) 1383 2'b00: wp[4] = match4; 1384 2'b01: wp[4] = match4 & wp[3]; 1385 2'b10: wp[4] = match4 | wp[3]; 1386 2'b11: wp[4] = 1'b0; 1387 endcase 1388 1389 // 1390 // Compare To What (Match Condition 5) 1391 // 1392 always @(dcr5 or id_pc or dcpu_adr_i or dcpu_dat_dc 1393 or dcpu_dat_lsu or dcpu_we_i) 1394 case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case 1395 3'b001: match_cond5_ct = id_pc; // insn fetch EA 1396 3'b010: match_cond5_ct = dcpu_adr_i; // load EA 1397 3'b011: match_cond5_ct = dcpu_adr_i; // store EA 1398 3'b100: match_cond5_ct = dcpu_dat_dc; // load data 1399 3'b101: match_cond5_ct = dcpu_dat_lsu; // store data 1400 3'b110: match_cond5_ct = dcpu_adr_i; // load/store EA 1401 default:match_cond5_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; 1402 endcase 1403 1404 // 1405 // When To Compare (Match Condition 5) 1406 // 1407 always @(dcr5 or dcpu_cycstb_i) 1408 case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case 1409 3'b000: match_cond5_stb = 1'b0; //comparison disabled 1410 3'b001: match_cond5_stb = 1'b1; // insn fetch EA 1411 default:match_cond5_stb = dcpu_cycstb_i; // any load/store 1412 endcase 1413 1414 // 1415 // Match Condition 5 1416 // 1417 always @(match_cond5_stb or dcr5 or dvr5 or match_cond5_ct) 1418 casex ({match_cond5_stb, dcr5[`OR1200_DU_DCR_CC]}) 1419 4'b0_xxx, 1420 4'b1_000, 1421 4'b1_111: match5 = 1'b0; 1422 4'b1_001: match5 = 1423 ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} == 1424 {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]}); 1425 4'b1_010: match5 = 1426 ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} < 1427 {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]}); 1428 4'b1_011: match5 = 1429 ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <= 1430 {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]}); 1431 4'b1_100: match5 = 1432 ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} > 1433 {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]}); 1434 4'b1_101: match5 = 1435 ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >= 1436 {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]}); 1437 4'b1_110: match5 = 1438 ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} != 1439 {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]}); 1440 endcase 1441 1442 // 1443 // Watchpoint 5 1444 // 1445 always @(dmr1 or match5 or wp) 1446 case (dmr1[`OR1200_DU_DMR1_CW5]) 1447 2'b00: wp[5] = match5; 1448 2'b01: wp[5] = match5 & wp[4]; 1449 2'b10: wp[5] = match5 | wp[4]; 1450 2'b11: wp[5] = 1'b0; 1451 endcase 1452 1453 // 1454 // Compare To What (Match Condition 6) 1455 // 1456 always @(dcr6 or id_pc or dcpu_adr_i or dcpu_dat_dc 1457 or dcpu_dat_lsu or dcpu_we_i) 1458 case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case 1459 3'b001: match_cond6_ct = id_pc; // insn fetch EA 1460 3'b010: match_cond6_ct = dcpu_adr_i; // load EA 1461 3'b011: match_cond6_ct = dcpu_adr_i; // store EA 1462 3'b100: match_cond6_ct = dcpu_dat_dc; // load data 1463 3'b101: match_cond6_ct = dcpu_dat_lsu; // store data 1464 3'b110: match_cond6_ct = dcpu_adr_i; // load/store EA 1465 default:match_cond6_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; 1466 endcase 1467 1468 // 1469 // When To Compare (Match Condition 6) 1470 // 1471 always @(dcr6 or dcpu_cycstb_i) 1472 case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case 1473 3'b000: match_cond6_stb = 1'b0; //comparison disabled 1474 3'b001: match_cond6_stb = 1'b1; // insn fetch EA 1475 default:match_cond6_stb = dcpu_cycstb_i; // any load/store 1476 endcase 1477 1478 // 1479 // Match Condition 6 1480 // 1481 always @(match_cond6_stb or dcr6 or dvr6 or match_cond6_ct) 1482 casex ({match_cond6_stb, dcr6[`OR1200_DU_DCR_CC]}) 1483 4'b0_xxx, 1484 4'b1_000, 1485 4'b1_111: match6 = 1'b0; 1486 4'b1_001: match6 = 1487 ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} == 1488 {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]}); 1489 4'b1_010: match6 = 1490 ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} < 1491 {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]}); 1492 4'b1_011: match6 = 1493 ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <= 1494 {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]}); 1495 4'b1_100: match6 = 1496 ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} > 1497 {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]}); 1498 4'b1_101: match6 = 1499 ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >= 1500 {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]}); 1501 4'b1_110: match6 = 1502 ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} != 1503 {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]}); 1504 endcase 1505 1506 // 1507 // Watchpoint 6 1508 // 1509 always @(dmr1 or match6 or wp) 1510 case (dmr1[`OR1200_DU_DMR1_CW6]) 1511 2'b00: wp[6] = match6; 1512 2'b01: wp[6] = match6 & wp[5]; 1513 2'b10: wp[6] = match6 | wp[5]; 1514 2'b11: wp[6] = 1'b0; 1515 endcase 1516 1517 // 1518 // Compare To What (Match Condition 7) 1519 // 1520 always @(dcr7 or id_pc or dcpu_adr_i or dcpu_dat_dc 1521 or dcpu_dat_lsu or dcpu_we_i) 1522 case (dcr7[`OR1200_DU_DCR_CT]) // synopsys parallel_case 1523 3'b001: match_cond7_ct = id_pc; // insn fetch EA 1524 3'b010: match_cond7_ct = dcpu_adr_i; // load EA 1525 3'b011: match_cond7_ct = dcpu_adr_i; // store EA 1526 3'b100: match_cond7_ct = dcpu_dat_dc; // load data 1527 3'b101: match_cond7_ct = dcpu_dat_lsu; // store data 1528 3'b110: match_cond7_ct = dcpu_adr_i; // load/store EA 1529 default:match_cond7_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; 1530 endcase 1531 1532 // 1533 // When To Compare (Match Condition 7) 1534 // 1535 always @(dcr7 or dcpu_cycstb_i) 1536 case (dcr7[`OR1200_DU_DCR_CT]) // synopsys parallel_case 1537 3'b000: match_cond7_stb = 1'b0; //comparison disabled 1538 3'b001: match_cond7_stb = 1'b1; // insn fetch EA 1539 default:match_cond7_stb = dcpu_cycstb_i; // any load/store 1540 endcase 1541 1542 // 1543 // Match Condition 7 1544 // 1545 always @(match_cond7_stb or dcr7 or dvr7 or match_cond7_ct) 1546 casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]}) 1547 4'b0_xxx, 1548 4'b1_000, 1549 4'b1_111: match7 = 1'b0; 1550 4'b1_001: match7 = 1551 ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} == 1552 {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]}); 1553 4'b1_010: match7 = 1554 ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} < 1555 {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]}); 1556 4'b1_011: match7 = 1557 ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <= 1558 {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]}); 1559 4'b1_100: match7 = 1560 ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} > 1561 {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]}); 1562 4'b1_101: match7 = 1563 ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >= 1564 {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]}); 1565 4'b1_110: match7 = 1566 ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} != 1567 {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]}); 1568 endcase 1569 1570 // 1571 // Watchpoint 7 1572 // 1573 always @(dmr1 or match7 or wp) 1574 case (dmr1[`OR1200_DU_DMR1_CW7]) 1575 2'b00: wp[7] = match7; 1576 2'b01: wp[7] = match7 & wp[6]; 1577 2'b10: wp[7] = match7 | wp[6]; 1578 2'b11: wp[7] = 1'b0; 1579 endcase 1580 1581 // 1582 // Increment Watchpoint Counter 0 1583 // 1584 always @(wp or dmr2) 1585 if (dmr2[`OR1200_DU_DMR2_WCE0]) 1586 incr_wpcntr0 = |(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]); 1587 else 1588 incr_wpcntr0 = 1'b0; 1589 1590 // 1591 // Match Condition Watchpoint Counter 0 1592 // 1593 always @(dwcr0) 1594 if (dwcr0[`OR1200_DU_DWCR_MATCH] == dwcr0[`OR1200_DU_DWCR_COUNT]) 1595 wpcntr0_match = 1'b1; 1596 else 1597 wpcntr0_match = 1'b0; 1598 1599 1600 // 1601 // Watchpoint 8 1602 // 1603 always @(dmr1 or wpcntr0_match or wp) 1604 case (dmr1[`OR1200_DU_DMR1_CW8]) 1605 2'b00: wp[8] = wpcntr0_match; 1606 2'b01: wp[8] = wpcntr0_match & wp[7]; 1607 2'b10: wp[8] = wpcntr0_match | wp[7]; 1608 2'b11: wp[8] = 1'b0; 1609 endcase 1610 1611 1612 // 1613 // Increment Watchpoint Counter 1 1614 // 1615 always @(wp or dmr2) 1616 if (dmr2[`OR1200_DU_DMR2_WCE1]) 1617 incr_wpcntr1 = |(wp & dmr2[`OR1200_DU_DMR2_AWTC]); 1618 else 1619 incr_wpcntr1 = 1'b0; 1620 1621 // 1622 // Match Condition Watchpoint Counter 1 1623 // 1624 always @(dwcr1) 1625 if (dwcr1[`OR1200_DU_DWCR_MATCH] == dwcr1[`OR1200_DU_DWCR_COUNT]) 1626 wpcntr1_match = 1'b1; 1627 else 1628 wpcntr1_match = 1'b0; 1629 1630 // 1631 // Watchpoint 9 1632 // 1633 always @(dmr1 or wpcntr1_match or wp) 1634 case (dmr1[`OR1200_DU_DMR1_CW9]) 1635 2'b00: wp[9] = wpcntr1_match; 1636 2'b01: wp[9] = wpcntr1_match & wp[8]; 1637 2'b10: wp[9] = wpcntr1_match | wp[8]; 1638 2'b11: wp[9] = 1'b0; 1639 endcase 1640 1641 // 1642 // Watchpoint 10 1643 // 1644 always @(dmr1 or dbg_ewt_i or wp) 1645 case (dmr1[`OR1200_DU_DMR1_CW10]) 1646 2'b00: wp[10] = dbg_ewt_i; 1647 2'b01: wp[10] = dbg_ewt_i & wp[9]; 1648 2'b10: wp[10] = dbg_ewt_i | wp[9]; 1649 2'b11: wp[10] = 1'b0; 1650 endcase 1651 1652 `endif 1653 1654 // 1655 // Watchpoints can cause trap exception 1656 // 1657 `ifdef OR1200_DU_HWBKPTS 1658 assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]) | du_hwbkpt_hold | (dbg_bp_r & ~dsr[`OR1200_DU_DSR_TE]); 1659 `else 1660 assign du_hwbkpt = 1'b0; 1661 `endif 1662 1663 // Hold du_hwbkpt if ex_freeze is active in order to cause trap exception 1664 always @(posedge clk or `OR1200_RST_EVENT rst) 1665 if (rst == `OR1200_RST_VALUE) 1666 du_hwbkpt_hold <= 1'b0; 1667 else if (du_hwbkpt & ex_freeze) 1668 du_hwbkpt_hold <= 1'b1; 1669 else if (!ex_freeze) 1670 du_hwbkpt_hold <= 1'b0; 1671 1672 `ifdef OR1200_DU_TB_IMPLEMENTED 1673 // 1674 // Simple trace buffer 1675 // (right now hardcoded for Xilinx Virtex FPGAs) 1676 // 1677 // Stores last 256 instruction addresses, instruction 1678 // machine words and ALU results 1679 // 1680 1681 // 1682 // Trace buffer write enable 1683 // 1684 assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]); 1685 1686 // 1687 // Trace buffer write address pointer 1688 // 1689 always @(posedge clk or `OR1200_RST_EVENT rst) 1690 if (rst == `OR1200_RST_VALUE) 1691 tb_wadr <= 8'h00; 1692 else if (tb_enw) 1693 tb_wadr <= tb_wadr + 8'd1; 1694 1695 // 1696 // Free running counter (time stamp) 1697 // 1698 always @(posedge clk or `OR1200_RST_EVENT rst) 1699 if (rst == `OR1200_RST_VALUE) 1700 tb_timstmp <= 32'h00000000; 1701 else if (!dbg_bp_r) 1702 tb_timstmp <= tb_timstmp + 32'd1; 1703 1704 // 1705 // Trace buffer RAMs 1706 // 1707 1708 or1200_dpram_256x32 tbia_ram( 1709 .clk_a(clk), 1710 .rst_a(1'b0), 1711 .addr_a(spr_addr[7:0]), 1712 .ce_a(1'b1), 1713 .oe_a(1'b1), 1714 .do_a(tbia_dat_o), 1715 1716 .clk_b(clk), 1717 .rst_b(1'b0), 1718 .addr_b(tb_wadr), 1719 .di_b(spr_dat_npc), 1720 .ce_b(1'b1), 1721 .we_b(tb_enw) 1722 1723 ); 1724 1725 or1200_dpram_256x32 tbim_ram( 1726 .clk_a(clk), 1727 .rst_a(1'b0), 1728 .addr_a(spr_addr[7:0]), 1729 .ce_a(1'b1), 1730 .oe_a(1'b1), 1731 .do_a(tbim_dat_o), 1732 1733 .clk_b(clk), 1734 .rst_b(1'b0), 1735 .addr_b(tb_wadr), 1736 .di_b(ex_insn), 1737 .ce_b(1'b1), 1738 .we_b(tb_enw) 1739 ); 1740 1741 or1200_dpram_256x32 tbar_ram( 1742 .clk_a(clk), 1743 .rst_a(1'b0), 1744 .addr_a(spr_addr[7:0]), 1745 .ce_a(1'b1), 1746 .oe_a(1'b1), 1747 .do_a(tbar_dat_o), 1748 1749 .clk_b(clk), 1750 .rst_b(1'b0), 1751 .addr_b(tb_wadr), 1752 .di_b(rf_dataw), 1753 .ce_b(1'b1), 1754 .we_b(tb_enw) 1755 ); 1756 1757 or1200_dpram_256x32 tbts_ram( 1758 .clk_a(clk), 1759 .rst_a(1'b0), 1760 .addr_a(spr_addr[7:0]), 1761 .ce_a(1'b1), 1762 .oe_a(1'b1), 1763 .do_a(tbts_dat_o), 1764 1765 .clk_b(clk), 1766 .rst_b(1'b0), 1767 .addr_b(tb_wadr), 1768 .di_b(tb_timstmp), 1769 .ce_b(1'b1), 1770 .we_b(tb_enw) 1771 ); 1772 1773 `else 1774 1775 assign tbia_dat_o = 32'h0000_0000; 1776 assign tbim_dat_o = 32'h0000_0000; 1777 assign tbar_dat_o = 32'h0000_0000; 1778 assign tbts_dat_o = 32'h0000_0000; 1779 1780 `endif // OR1200_DU_TB_IMPLEMENTED 1781 1782 `else // OR1200_DU_IMPLEMENTED 1783 1784 // 1785 // When DU is not implemented, drive all outputs as would when DU is disabled 1786 // 1787 assign dbg_bp_o = 1'b0; 1788 assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}}; 1789 assign du_dmr1 = {25{1'b0}}; 1790 assign du_hwbkpt = 1'b0; 1791 1792 // 1793 // Read DU registers 1794 // 1795 `ifdef OR1200_DU_READREGS 1796 assign spr_dat_o = 32'h0000_0000; 1797 `ifdef OR1200_DU_UNUSED_ZERO 1798 `endif 1799 `endif 1800 1801 `endif 1802 1803 endmodule