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0001 <!DOCTYPE html> 0002 <html><head> 0003 <meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/> 0004 <title>or1200_du.v</title> 0005 <meta name="generator" content="KF5::SyntaxHighlighting - Definition (Verilog) - Theme (Breeze Dark)"/> 0006 </head><body style="background-color:#232629;color:#cfcfc2"><pre> 0007 <span style="color:#7a7c7d">//////////////////////////////////////////////////////////////////////</span> 0008 <span style="color:#7a7c7d">//// ////</span> 0009 <span style="color:#7a7c7d">//// OR1200's Debug Unit ////</span> 0010 <span style="color:#7a7c7d">//// ////</span> 0011 <span style="color:#7a7c7d">//// This file is part of the OpenRISC 1200 project ////</span> 0012 <span style="color:#7a7c7d">//// http://www.opencores.org/project,or1k ////</span> 0013 <span style="color:#7a7c7d">//// ////</span> 0014 <span style="color:#7a7c7d">//// Description ////</span> 0015 <span style="color:#7a7c7d">//// Basic OR1200 debug unit. ////</span> 0016 <span style="color:#7a7c7d">//// ////</span> 0017 <span style="color:#7a7c7d">//// To Do: ////</span> 0018 <span style="color:#7a7c7d">//// - make it smaller and faster ////</span> 0019 <span style="color:#7a7c7d">//// ////</span> 0020 <span style="color:#7a7c7d">//// Author(s): ////</span> 0021 <span style="color:#7a7c7d">//// - Damjan Lampret, lampret@opencores.org ////</span> 0022 <span style="color:#7a7c7d">//// ////</span> 0023 <span style="color:#7a7c7d">//////////////////////////////////////////////////////////////////////</span> 0024 <span style="color:#7a7c7d">//// ////</span> 0025 <span style="color:#7a7c7d">//// Copyright (C) 2000 Authors and OPENCORES.ORG ////</span> 0026 <span style="color:#7a7c7d">//// ////</span> 0027 <span style="color:#7a7c7d">//// This source file may be used and distributed without ////</span> 0028 <span style="color:#7a7c7d">//// restriction provided that this copyright statement is not ////</span> 0029 <span style="color:#7a7c7d">//// removed from the file and that any derivative work contains ////</span> 0030 <span style="color:#7a7c7d">//// the original copyright notice and the associated disclaimer. ////</span> 0031 <span style="color:#7a7c7d">//// ////</span> 0032 <span style="color:#7a7c7d">//// This source file is free software; you can redistribute it ////</span> 0033 <span style="color:#7a7c7d">//// and/or modify it under the terms of the GNU Lesser General ////</span> 0034 <span style="color:#7a7c7d">//// Public License as published by the Free Software Foundation; ////</span> 0035 <span style="color:#7a7c7d">//// either version 2.1 of the License, or (at your option) any ////</span> 0036 <span style="color:#7a7c7d">//// later version. ////</span> 0037 <span style="color:#7a7c7d">//// ////</span> 0038 <span style="color:#7a7c7d">//// This source is distributed in the hope that it will be ////</span> 0039 <span style="color:#7a7c7d">//// useful, but WITHOUT ANY WARRANTY; without even the implied ////</span> 0040 <span style="color:#7a7c7d">//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////</span> 0041 <span style="color:#7a7c7d">//// PURPOSE. See the GNU Lesser General Public License for more ////</span> 0042 <span style="color:#7a7c7d">//// details. ////</span> 0043 <span style="color:#7a7c7d">//// ////</span> 0044 <span style="color:#7a7c7d">//// You should have received a copy of the GNU Lesser General ////</span> 0045 <span style="color:#7a7c7d">//// Public License along with this source; if not, download it ////</span> 0046 <span style="color:#7a7c7d">//// from http://www.opencores.org/lgpl.shtml ////</span> 0047 <span style="color:#7a7c7d">//// ////</span> 0048 <span style="color:#7a7c7d">//////////////////////////////////////////////////////////////////////</span> 0049 <span style="color:#7a7c7d">//</span> 0050 <span style="color:#7a7c7d">//</span> 0051 <span style="color:#7a7c7d">// $Log: or1200_du.v,v $</span> 0052 <span style="color:#7a7c7d">// Revision 2.0 2010/06/30 11:00:00 ORSoC</span> 0053 <span style="color:#7a7c7d">// Minor update: </span> 0054 <span style="color:#7a7c7d">// Bugs fixed. </span> 0055 0056 <span style="color:#7a7c7d">// synopsys translate_off</span> 0057 <span style="color:#27ae60">`include </span><span style="color:#f67400">"timescale.v"</span> 0058 <span style="color:#7a7c7d">// synopsys translate_on</span> 0059 <span style="color:#27ae60">`include </span><span style="color:#f67400">"or1200_defines.v"</span> 0060 0061 <span style="color:#7a7c7d">//</span> 0062 <span style="color:#7a7c7d">// Debug unit</span> 0063 <span style="color:#7a7c7d">//</span> 0064 0065 <span style="font-weight:bold">module</span> or1200_du<span style="color:#3f8058">(</span> 0066 <span style="color:#7a7c7d">// RISC Internal Interface</span> 0067 clk<span style="color:#3f8058">,</span> rst<span style="color:#3f8058">,</span> 0068 dcpu_cycstb_i<span style="color:#3f8058">,</span> dcpu_we_i<span style="color:#3f8058">,</span> dcpu_adr_i<span style="color:#3f8058">,</span> dcpu_dat_lsu<span style="color:#3f8058">,</span> 0069 dcpu_dat_dc<span style="color:#3f8058">,</span> icpu_cycstb_i<span style="color:#3f8058">,</span> 0070 ex_freeze<span style="color:#3f8058">,</span> branch_op<span style="color:#3f8058">,</span> ex_insn<span style="color:#3f8058">,</span> id_pc<span style="color:#3f8058">,</span> 0071 spr_dat_npc<span style="color:#3f8058">,</span> rf_dataw<span style="color:#3f8058">,</span> 0072 du_dsr<span style="color:#3f8058">,</span> du_dmr1<span style="color:#3f8058">,</span> du_stall<span style="color:#3f8058">,</span> du_addr<span style="color:#3f8058">,</span> du_dat_i<span style="color:#3f8058">,</span> du_dat_o<span style="color:#3f8058">,</span> 0073 du_read<span style="color:#3f8058">,</span> du_write<span style="color:#3f8058">,</span> du_except_stop<span style="color:#3f8058">,</span> du_hwbkpt<span style="color:#3f8058">,</span> du_flush_pipe<span style="color:#3f8058">,</span> 0074 spr_cs<span style="color:#3f8058">,</span> spr_write<span style="color:#3f8058">,</span> spr_addr<span style="color:#3f8058">,</span> spr_dat_i<span style="color:#3f8058">,</span> spr_dat_o<span style="color:#3f8058">,</span> 0075 0076 <span style="color:#7a7c7d">// External Debug Interface</span> 0077 dbg_stall_i<span style="color:#3f8058">,</span> dbg_ewt_i<span style="color:#3f8058">,</span> dbg_lss_o<span style="color:#3f8058">,</span> dbg_is_o<span style="color:#3f8058">,</span> dbg_wp_o<span style="color:#3f8058">,</span> dbg_bp_o<span style="color:#3f8058">,</span> 0078 dbg_stb_i<span style="color:#3f8058">,</span> dbg_we_i<span style="color:#3f8058">,</span> dbg_adr_i<span style="color:#3f8058">,</span> dbg_dat_i<span style="color:#3f8058">,</span> dbg_dat_o<span style="color:#3f8058">,</span> dbg_ack_o 0079 <span style="color:#3f8058">);</span> 0080 0081 <span style="color:#2980b9">parameter</span> dw <span style="color:#3f8058">=</span> <span style="color:#27ae60">`OR1200_OPERAND_WIDTH</span><span style="color:#3f8058">;</span> 0082 <span style="color:#2980b9">parameter</span> aw <span style="color:#3f8058">=</span> <span style="color:#27ae60">`OR1200_OPERAND_WIDTH</span><span style="color:#3f8058">;</span> 0083 0084 <span style="color:#7a7c7d">//</span> 0085 <span style="color:#7a7c7d">// I/O</span> 0086 <span style="color:#7a7c7d">//</span> 0087 0088 <span style="color:#7a7c7d">//</span> 0089 <span style="color:#7a7c7d">// RISC Internal Interface</span> 0090 <span style="color:#7a7c7d">//</span> 0091 <span style="color:#2980b9">input</span> clk<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// Clock</span> 0092 <span style="color:#2980b9">input</span> rst<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// Reset</span> 0093 <span style="color:#2980b9">input</span> dcpu_cycstb_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// LSU status</span> 0094 <span style="color:#2980b9">input</span> dcpu_we_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// LSU status</span> 0095 <span style="color:#2980b9">input</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// LSU addr</span> 0096 <span style="color:#2980b9">input</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcpu_dat_lsu<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// LSU store data</span> 0097 <span style="color:#2980b9">input</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcpu_dat_dc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// LSU load data</span> 0098 <span style="color:#2980b9">input</span> <span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_FETCHOP_WIDTH</span><span style="color:#3f8058">-</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> icpu_cycstb_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// IFETCH unit status</span> 0099 <span style="color:#2980b9">input</span> ex_freeze<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// EX stage freeze</span> 0100 <span style="color:#2980b9">input</span> <span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_BRANCHOP_WIDTH</span><span style="color:#3f8058">-</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> branch_op<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// Branch op</span> 0101 <span style="color:#2980b9">input</span> <span style="color:#3f8058">[</span>dw<span style="color:#3f8058">-</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> ex_insn<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// EX insn</span> 0102 <span style="color:#2980b9">input</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> id_pc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// insn fetch EA</span> 0103 <span style="color:#2980b9">input</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> spr_dat_npc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// Next PC (for trace)</span> 0104 <span style="color:#2980b9">input</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> rf_dataw<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// ALU result (for trace)</span> 0105 <span style="color:#2980b9">output</span> <span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DSR_WIDTH</span><span style="color:#3f8058">-</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> du_dsr<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// DSR</span> 0106 <span style="color:#2980b9">output</span> <span style="color:#3f8058">[</span><span style="color:#f67400">24</span><span style="color:#3f8058">:</span> <span style="color:#f67400">0</span><span style="color:#3f8058">]</span> du_dmr1<span style="color:#3f8058">;</span> 0107 <span style="color:#2980b9">output</span> du_stall<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// Debug Unit Stall</span> 0108 <span style="color:#2980b9">output</span> <span style="color:#3f8058">[</span>aw<span style="color:#3f8058">-</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> du_addr<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// Debug Unit Address</span> 0109 <span style="color:#2980b9">input</span> <span style="color:#3f8058">[</span>dw<span style="color:#3f8058">-</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> du_dat_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// Debug Unit Data In</span> 0110 <span style="color:#2980b9">output</span> <span style="color:#3f8058">[</span>dw<span style="color:#3f8058">-</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> du_dat_o<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// Debug Unit Data Out</span> 0111 <span style="color:#2980b9">output</span> du_read<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// Debug Unit Read Enable</span> 0112 <span style="color:#2980b9">output</span> du_write<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// Debug Unit Write Enable</span> 0113 <span style="color:#2980b9">input</span> <span style="color:#3f8058">[</span><span style="color:#f67400">13</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> du_except_stop<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// Exception masked by DSR</span> 0114 <span style="color:#2980b9">output</span> du_hwbkpt<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// Cause trap exception (HW Breakpoints)</span> 0115 <span style="color:#2980b9">output</span> du_flush_pipe<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// Cause pipeline flush and pc<-npc</span> 0116 <span style="color:#2980b9">input</span> spr_cs<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// SPR Chip Select</span> 0117 <span style="color:#2980b9">input</span> spr_write<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// SPR Read/Write</span> 0118 <span style="color:#2980b9">input</span> <span style="color:#3f8058">[</span>aw<span style="color:#3f8058">-</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> spr_addr<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// SPR Address</span> 0119 <span style="color:#2980b9">input</span> <span style="color:#3f8058">[</span>dw<span style="color:#3f8058">-</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> spr_dat_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// SPR Data Input</span> 0120 <span style="color:#2980b9">output</span> <span style="color:#3f8058">[</span>dw<span style="color:#3f8058">-</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> spr_dat_o<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// SPR Data Output</span> 0121 0122 <span style="color:#7a7c7d">//</span> 0123 <span style="color:#7a7c7d">// External Debug Interface</span> 0124 <span style="color:#7a7c7d">//</span> 0125 <span style="color:#2980b9">input</span> dbg_stall_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// External Stall Input</span> 0126 <span style="color:#2980b9">input</span> dbg_ewt_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// External Watchpoint Trigger Input</span> 0127 <span style="color:#2980b9">output</span> <span style="color:#3f8058">[</span><span style="color:#f67400">3</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dbg_lss_o<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// External Load/Store Unit Status</span> 0128 <span style="color:#2980b9">output</span> <span style="color:#3f8058">[</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dbg_is_o<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// External Insn Fetch Status</span> 0129 <span style="color:#2980b9">output</span> <span style="color:#3f8058">[</span><span style="color:#f67400">10</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dbg_wp_o<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// Watchpoints Outputs</span> 0130 <span style="color:#2980b9">output</span> dbg_bp_o<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// Breakpoint Output</span> 0131 <span style="color:#2980b9">input</span> dbg_stb_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// External Address/Data Strobe</span> 0132 <span style="color:#2980b9">input</span> dbg_we_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// External Write Enable</span> 0133 <span style="color:#2980b9">input</span> <span style="color:#3f8058">[</span>aw<span style="color:#3f8058">-</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dbg_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// External Address Input</span> 0134 <span style="color:#2980b9">input</span> <span style="color:#3f8058">[</span>dw<span style="color:#3f8058">-</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dbg_dat_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// External Data Input</span> 0135 <span style="color:#2980b9">output</span> <span style="color:#3f8058">[</span>dw<span style="color:#3f8058">-</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dbg_dat_o<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// External Data Output</span> 0136 <span style="color:#2980b9">output</span> dbg_ack_o<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// External Data Acknowledge (not WB compatible)</span> 0137 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span>dw<span style="color:#3f8058">-</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dbg_dat_o<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// External Data Output</span> 0138 <span style="color:#2980b9">reg</span> dbg_ack_o<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// External Data Acknowledge (not WB compatible)</span> 0139 0140 0141 <span style="color:#7a7c7d">//</span> 0142 <span style="color:#7a7c7d">// Some connections go directly from the CPU through DU to Debug I/F</span> 0143 <span style="color:#7a7c7d">//</span> 0144 <span style="color:#27ae60">`ifdef OR1200_DU_STATUS_UNIMPLEMENTED</span> 0145 <span style="font-weight:bold">assign</span> dbg_lss_o <span style="color:#3f8058">=</span> <span style="color:#f67400">4'b0000</span><span style="color:#3f8058">;</span> 0146 0147 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dbg_is_o<span style="color:#3f8058">;</span> 0148 <span style="color:#7a7c7d">//</span> 0149 <span style="color:#7a7c7d">// Show insn activity (temp, must be removed)</span> 0150 <span style="color:#7a7c7d">//</span> 0151 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0152 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0153 dbg_is_o <span style="color:#3f8058"><=</span> <span style="color:#f67400">2'b00</span><span style="color:#3f8058">;</span> 0154 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(!</span>ex_freeze <span style="color:#3f8058">&</span> <span style="color:#3f8058">~((</span>ex_insn<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">26</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_OR32_NOP</span><span style="color:#3f8058">)</span> <span style="color:#3f8058">&</span> ex_insn<span style="color:#3f8058">[</span><span style="color:#f67400">16</span><span style="color:#3f8058">]))</span> 0155 dbg_is_o <span style="color:#3f8058"><=</span> <span style="color:#3f8058">~</span>dbg_is_o<span style="color:#3f8058">;</span> 0156 <span style="color:#27ae60">`ifdef UNUSED</span> 0157 <span style="font-weight:bold">assign</span> dbg_is_o <span style="color:#3f8058">=</span> <span style="color:#f67400">2'b00</span><span style="color:#3f8058">;</span> 0158 <span style="color:#27ae60">`endif</span> 0159 <span style="color:#27ae60">`else</span> 0160 <span style="font-weight:bold">assign</span> dbg_lss_o <span style="color:#3f8058">=</span> dcpu_cycstb_i <span style="color:#3f8058">?</span> <span style="color:#3f8058">{</span>dcpu_we_i<span style="color:#3f8058">,</span> <span style="color:#f67400">3'b000</span><span style="color:#3f8058">}</span> <span style="color:#3f8058">:</span> <span style="color:#f67400">4'b0000</span><span style="color:#3f8058">;</span> 0161 <span style="font-weight:bold">assign</span> dbg_is_o <span style="color:#3f8058">=</span> <span style="color:#3f8058">{</span><span style="color:#f67400">1'b0</span><span style="color:#3f8058">,</span> icpu_cycstb_i<span style="color:#3f8058">};</span> 0162 <span style="color:#27ae60">`endif</span> 0163 <span style="font-weight:bold">assign</span> dbg_wp_o <span style="color:#3f8058">=</span> <span style="color:#f67400">11'b000_0000_0000</span><span style="color:#3f8058">;</span> 0164 0165 <span style="color:#7a7c7d">//</span> 0166 <span style="color:#7a7c7d">// Some connections go directly from Debug I/F through DU to the CPU</span> 0167 <span style="color:#7a7c7d">//</span> 0168 <span style="font-weight:bold">assign</span> du_stall <span style="color:#3f8058">=</span> dbg_stall_i<span style="color:#3f8058">;</span> 0169 <span style="font-weight:bold">assign</span> du_addr <span style="color:#3f8058">=</span> dbg_adr_i<span style="color:#3f8058">;</span> 0170 <span style="font-weight:bold">assign</span> du_dat_o <span style="color:#3f8058">=</span> dbg_dat_i<span style="color:#3f8058">;</span> 0171 <span style="font-weight:bold">assign</span> du_read <span style="color:#3f8058">=</span> dbg_stb_i <span style="color:#3f8058">&&</span> <span style="color:#3f8058">!</span>dbg_we_i<span style="color:#3f8058">;</span> 0172 <span style="font-weight:bold">assign</span> du_write <span style="color:#3f8058">=</span> dbg_stb_i <span style="color:#3f8058">&&</span> dbg_we_i<span style="color:#3f8058">;</span> 0173 0174 <span style="color:#7a7c7d">//</span> 0175 <span style="color:#7a7c7d">// After a sw breakpoint, the replaced instruction need to be executed.</span> 0176 <span style="color:#7a7c7d">// We flush the entire pipeline and set the pc to the current address</span> 0177 <span style="color:#7a7c7d">// to execute the restored address.</span> 0178 <span style="color:#7a7c7d">//</span> 0179 0180 <span style="color:#2980b9">reg</span> du_flush_pipe_r<span style="color:#3f8058">;</span> 0181 <span style="color:#2980b9">reg</span> dbg_stall_i_r<span style="color:#3f8058">;</span> 0182 0183 <span style="font-weight:bold">assign</span> du_flush_pipe <span style="color:#3f8058">=</span> du_flush_pipe_r<span style="color:#3f8058">;</span> 0184 0185 <span style="color:#7a7c7d">//</span> 0186 <span style="color:#7a7c7d">// Register du_flush_pipe</span> 0187 <span style="color:#7a7c7d">//</span> 0188 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> <span style="font-weight:bold">begin</span> 0189 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> <span style="font-weight:bold">begin</span> 0190 du_flush_pipe_r <span style="color:#3f8058"><=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 0191 <span style="font-weight:bold">end</span> 0192 <span style="font-weight:bold">else</span> <span style="font-weight:bold">begin</span> 0193 du_flush_pipe_r <span style="color:#3f8058"><=</span> <span style="color:#3f8058">(</span>dbg_stall_i_r <span style="color:#3f8058">&&</span> <span style="color:#3f8058">!</span>dbg_stall_i <span style="color:#3f8058">&&</span> <span style="color:#3f8058">|</span>du_except_stop<span style="color:#3f8058">);</span> 0194 <span style="font-weight:bold">end</span> 0195 <span style="font-weight:bold">end</span> 0196 0197 <span style="color:#7a7c7d">//</span> 0198 <span style="color:#7a7c7d">// Detect dbg_stall falling edge</span> 0199 <span style="color:#7a7c7d">//</span> 0200 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> <span style="font-weight:bold">begin</span> 0201 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> <span style="font-weight:bold">begin</span> 0202 dbg_stall_i_r <span style="color:#3f8058"><=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 0203 <span style="font-weight:bold">end</span> 0204 <span style="font-weight:bold">else</span> <span style="font-weight:bold">begin</span> 0205 dbg_stall_i_r <span style="color:#3f8058"><=</span> dbg_stall_i<span style="color:#3f8058">;</span> 0206 <span style="font-weight:bold">end</span> 0207 <span style="font-weight:bold">end</span> 0208 0209 <span style="color:#2980b9">reg</span> dbg_ack<span style="color:#3f8058">;</span> 0210 <span style="color:#7a7c7d">//</span> 0211 <span style="color:#7a7c7d">// Generate acknowledge -- just delay stb signal</span> 0212 <span style="color:#7a7c7d">//</span> 0213 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> <span style="font-weight:bold">begin</span> 0214 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> <span style="font-weight:bold">begin</span> 0215 dbg_ack <span style="color:#3f8058"><=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 0216 dbg_ack_o <span style="color:#3f8058"><=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 0217 <span style="font-weight:bold">end</span> 0218 <span style="font-weight:bold">else</span> <span style="font-weight:bold">begin</span> 0219 dbg_ack <span style="color:#3f8058"><=</span> dbg_stb_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// valid when du_dat_i </span> 0220 dbg_ack_o <span style="color:#3f8058"><=</span> dbg_ack <span style="color:#3f8058">&</span> dbg_stb_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// valid when dbg_dat_o </span> 0221 <span style="font-weight:bold">end</span> 0222 <span style="font-weight:bold">end</span> 0223 0224 <span style="color:#7a7c7d">// </span> 0225 <span style="color:#7a7c7d">// Register data output</span> 0226 <span style="color:#7a7c7d">//</span> 0227 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk<span style="color:#3f8058">)</span> 0228 dbg_dat_o <span style="color:#3f8058"><=</span> du_dat_i<span style="color:#3f8058">;</span> 0229 0230 <span style="color:#27ae60">`ifdef OR1200_DU_IMPLEMENTED</span> 0231 0232 <span style="color:#7a7c7d">//</span> 0233 <span style="color:#7a7c7d">// Debug Mode Register 1</span> 0234 <span style="color:#7a7c7d">//</span> 0235 <span style="color:#27ae60">`ifdef OR1200_DU_DMR1</span> 0236 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">24</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dmr1<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// DMR1 implemented</span> 0237 <span style="color:#27ae60">`else</span> 0238 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">24</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dmr1<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// DMR1 not implemented</span> 0239 <span style="color:#27ae60">`endif</span> 0240 <span style="font-weight:bold">assign</span> du_dmr1 <span style="color:#3f8058">=</span> dmr1<span style="color:#3f8058">;</span> 0241 0242 <span style="color:#7a7c7d">//</span> 0243 <span style="color:#7a7c7d">// Debug Mode Register 2</span> 0244 <span style="color:#7a7c7d">//</span> 0245 <span style="color:#27ae60">`ifdef OR1200_DU_DMR2</span> 0246 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">23</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dmr2<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// DMR2 implemented</span> 0247 <span style="color:#27ae60">`else</span> 0248 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">23</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dmr2<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// DMR2 not implemented</span> 0249 <span style="color:#27ae60">`endif</span> 0250 0251 <span style="color:#7a7c7d">//</span> 0252 <span style="color:#7a7c7d">// Debug Stop Register</span> 0253 <span style="color:#7a7c7d">//</span> 0254 <span style="color:#27ae60">`ifdef OR1200_DU_DSR</span> 0255 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DSR_WIDTH</span><span style="color:#3f8058">-</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dsr<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// DSR implemented</span> 0256 <span style="color:#27ae60">`else</span> 0257 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DSR_WIDTH</span><span style="color:#3f8058">-</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dsr<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// DSR not implemented</span> 0258 <span style="color:#27ae60">`endif</span> 0259 0260 <span style="color:#7a7c7d">//</span> 0261 <span style="color:#7a7c7d">// Debug Reason Register</span> 0262 <span style="color:#7a7c7d">//</span> 0263 <span style="color:#27ae60">`ifdef OR1200_DU_DRR</span> 0264 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">13</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> drr<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// DRR implemented</span> 0265 <span style="color:#27ae60">`else</span> 0266 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">13</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> drr<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// DRR not implemented</span> 0267 <span style="color:#27ae60">`endif</span> 0268 0269 <span style="color:#7a7c7d">//</span> 0270 <span style="color:#7a7c7d">// Debug Value Register N</span> 0271 <span style="color:#7a7c7d">//</span> 0272 <span style="color:#27ae60">`ifdef OR1200_DU_DVR0</span> 0273 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dvr0<span style="color:#3f8058">;</span> 0274 <span style="color:#27ae60">`else</span> 0275 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dvr0<span style="color:#3f8058">;</span> 0276 <span style="color:#27ae60">`endif</span> 0277 0278 <span style="color:#7a7c7d">//</span> 0279 <span style="color:#7a7c7d">// Debug Value Register N</span> 0280 <span style="color:#7a7c7d">//</span> 0281 <span style="color:#27ae60">`ifdef OR1200_DU_DVR1</span> 0282 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dvr1<span style="color:#3f8058">;</span> 0283 <span style="color:#27ae60">`else</span> 0284 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dvr1<span style="color:#3f8058">;</span> 0285 <span style="color:#27ae60">`endif</span> 0286 0287 <span style="color:#7a7c7d">//</span> 0288 <span style="color:#7a7c7d">// Debug Value Register N</span> 0289 <span style="color:#7a7c7d">//</span> 0290 <span style="color:#27ae60">`ifdef OR1200_DU_DVR2</span> 0291 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dvr2<span style="color:#3f8058">;</span> 0292 <span style="color:#27ae60">`else</span> 0293 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dvr2<span style="color:#3f8058">;</span> 0294 <span style="color:#27ae60">`endif</span> 0295 0296 <span style="color:#7a7c7d">//</span> 0297 <span style="color:#7a7c7d">// Debug Value Register N</span> 0298 <span style="color:#7a7c7d">//</span> 0299 <span style="color:#27ae60">`ifdef OR1200_DU_DVR3</span> 0300 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dvr3<span style="color:#3f8058">;</span> 0301 <span style="color:#27ae60">`else</span> 0302 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dvr3<span style="color:#3f8058">;</span> 0303 <span style="color:#27ae60">`endif</span> 0304 0305 <span style="color:#7a7c7d">//</span> 0306 <span style="color:#7a7c7d">// Debug Value Register N</span> 0307 <span style="color:#7a7c7d">//</span> 0308 <span style="color:#27ae60">`ifdef OR1200_DU_DVR4</span> 0309 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dvr4<span style="color:#3f8058">;</span> 0310 <span style="color:#27ae60">`else</span> 0311 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dvr4<span style="color:#3f8058">;</span> 0312 <span style="color:#27ae60">`endif</span> 0313 0314 <span style="color:#7a7c7d">//</span> 0315 <span style="color:#7a7c7d">// Debug Value Register N</span> 0316 <span style="color:#7a7c7d">//</span> 0317 <span style="color:#27ae60">`ifdef OR1200_DU_DVR5</span> 0318 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dvr5<span style="color:#3f8058">;</span> 0319 <span style="color:#27ae60">`else</span> 0320 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dvr5<span style="color:#3f8058">;</span> 0321 <span style="color:#27ae60">`endif</span> 0322 0323 <span style="color:#7a7c7d">//</span> 0324 <span style="color:#7a7c7d">// Debug Value Register N</span> 0325 <span style="color:#7a7c7d">//</span> 0326 <span style="color:#27ae60">`ifdef OR1200_DU_DVR6</span> 0327 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dvr6<span style="color:#3f8058">;</span> 0328 <span style="color:#27ae60">`else</span> 0329 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dvr6<span style="color:#3f8058">;</span> 0330 <span style="color:#27ae60">`endif</span> 0331 0332 <span style="color:#7a7c7d">//</span> 0333 <span style="color:#7a7c7d">// Debug Value Register N</span> 0334 <span style="color:#7a7c7d">//</span> 0335 <span style="color:#27ae60">`ifdef OR1200_DU_DVR7</span> 0336 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dvr7<span style="color:#3f8058">;</span> 0337 <span style="color:#27ae60">`else</span> 0338 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dvr7<span style="color:#3f8058">;</span> 0339 <span style="color:#27ae60">`endif</span> 0340 0341 <span style="color:#7a7c7d">//</span> 0342 <span style="color:#7a7c7d">// Debug Control Register N</span> 0343 <span style="color:#7a7c7d">//</span> 0344 <span style="color:#27ae60">`ifdef OR1200_DU_DCR0</span> 0345 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcr0<span style="color:#3f8058">;</span> 0346 <span style="color:#27ae60">`else</span> 0347 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcr0<span style="color:#3f8058">;</span> 0348 <span style="color:#27ae60">`endif</span> 0349 0350 <span style="color:#7a7c7d">//</span> 0351 <span style="color:#7a7c7d">// Debug Control Register N</span> 0352 <span style="color:#7a7c7d">//</span> 0353 <span style="color:#27ae60">`ifdef OR1200_DU_DCR1</span> 0354 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcr1<span style="color:#3f8058">;</span> 0355 <span style="color:#27ae60">`else</span> 0356 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcr1<span style="color:#3f8058">;</span> 0357 <span style="color:#27ae60">`endif</span> 0358 0359 <span style="color:#7a7c7d">//</span> 0360 <span style="color:#7a7c7d">// Debug Control Register N</span> 0361 <span style="color:#7a7c7d">//</span> 0362 <span style="color:#27ae60">`ifdef OR1200_DU_DCR2</span> 0363 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcr2<span style="color:#3f8058">;</span> 0364 <span style="color:#27ae60">`else</span> 0365 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcr2<span style="color:#3f8058">;</span> 0366 <span style="color:#27ae60">`endif</span> 0367 0368 <span style="color:#7a7c7d">//</span> 0369 <span style="color:#7a7c7d">// Debug Control Register N</span> 0370 <span style="color:#7a7c7d">//</span> 0371 <span style="color:#27ae60">`ifdef OR1200_DU_DCR3</span> 0372 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcr3<span style="color:#3f8058">;</span> 0373 <span style="color:#27ae60">`else</span> 0374 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcr3<span style="color:#3f8058">;</span> 0375 <span style="color:#27ae60">`endif</span> 0376 0377 <span style="color:#7a7c7d">//</span> 0378 <span style="color:#7a7c7d">// Debug Control Register N</span> 0379 <span style="color:#7a7c7d">//</span> 0380 <span style="color:#27ae60">`ifdef OR1200_DU_DCR4</span> 0381 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcr4<span style="color:#3f8058">;</span> 0382 <span style="color:#27ae60">`else</span> 0383 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcr4<span style="color:#3f8058">;</span> 0384 <span style="color:#27ae60">`endif</span> 0385 0386 <span style="color:#7a7c7d">//</span> 0387 <span style="color:#7a7c7d">// Debug Control Register N</span> 0388 <span style="color:#7a7c7d">//</span> 0389 <span style="color:#27ae60">`ifdef OR1200_DU_DCR5</span> 0390 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcr5<span style="color:#3f8058">;</span> 0391 <span style="color:#27ae60">`else</span> 0392 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcr5<span style="color:#3f8058">;</span> 0393 <span style="color:#27ae60">`endif</span> 0394 0395 <span style="color:#7a7c7d">//</span> 0396 <span style="color:#7a7c7d">// Debug Control Register N</span> 0397 <span style="color:#7a7c7d">//</span> 0398 <span style="color:#27ae60">`ifdef OR1200_DU_DCR6</span> 0399 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcr6<span style="color:#3f8058">;</span> 0400 <span style="color:#27ae60">`else</span> 0401 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcr6<span style="color:#3f8058">;</span> 0402 <span style="color:#27ae60">`endif</span> 0403 0404 <span style="color:#7a7c7d">//</span> 0405 <span style="color:#7a7c7d">// Debug Control Register N</span> 0406 <span style="color:#7a7c7d">//</span> 0407 <span style="color:#27ae60">`ifdef OR1200_DU_DCR7</span> 0408 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcr7<span style="color:#3f8058">;</span> 0409 <span style="color:#27ae60">`else</span> 0410 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dcr7<span style="color:#3f8058">;</span> 0411 <span style="color:#27ae60">`endif</span> 0412 0413 <span style="color:#7a7c7d">//</span> 0414 <span style="color:#7a7c7d">// Debug Watchpoint Counter Register 0</span> 0415 <span style="color:#7a7c7d">//</span> 0416 <span style="color:#27ae60">`ifdef OR1200_DU_DWCR0</span> 0417 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dwcr0<span style="color:#3f8058">;</span> 0418 <span style="color:#27ae60">`else</span> 0419 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dwcr0<span style="color:#3f8058">;</span> 0420 <span style="color:#27ae60">`endif</span> 0421 0422 <span style="color:#7a7c7d">//</span> 0423 <span style="color:#7a7c7d">// Debug Watchpoint Counter Register 1</span> 0424 <span style="color:#7a7c7d">//</span> 0425 <span style="color:#27ae60">`ifdef OR1200_DU_DWCR1</span> 0426 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dwcr1<span style="color:#3f8058">;</span> 0427 <span style="color:#27ae60">`else</span> 0428 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> dwcr1<span style="color:#3f8058">;</span> 0429 <span style="color:#27ae60">`endif</span> 0430 0431 <span style="color:#7a7c7d">//</span> 0432 <span style="color:#7a7c7d">// Internal wires</span> 0433 <span style="color:#7a7c7d">//</span> 0434 <span style="color:#2980b9">wire</span> dmr1_sel<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// DMR1 select</span> 0435 <span style="color:#2980b9">wire</span> dmr2_sel<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// DMR2 select</span> 0436 <span style="color:#2980b9">wire</span> dsr_sel<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// DSR select</span> 0437 <span style="color:#2980b9">wire</span> drr_sel<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// DRR select</span> 0438 <span style="color:#2980b9">wire</span> dvr0_sel<span style="color:#3f8058">,</span> 0439 dvr1_sel<span style="color:#3f8058">,</span> 0440 dvr2_sel<span style="color:#3f8058">,</span> 0441 dvr3_sel<span style="color:#3f8058">,</span> 0442 dvr4_sel<span style="color:#3f8058">,</span> 0443 dvr5_sel<span style="color:#3f8058">,</span> 0444 dvr6_sel<span style="color:#3f8058">,</span> 0445 dvr7_sel<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// DVR selects</span> 0446 <span style="color:#2980b9">wire</span> dcr0_sel<span style="color:#3f8058">,</span> 0447 dcr1_sel<span style="color:#3f8058">,</span> 0448 dcr2_sel<span style="color:#3f8058">,</span> 0449 dcr3_sel<span style="color:#3f8058">,</span> 0450 dcr4_sel<span style="color:#3f8058">,</span> 0451 dcr5_sel<span style="color:#3f8058">,</span> 0452 dcr6_sel<span style="color:#3f8058">,</span> 0453 dcr7_sel<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// DCR selects</span> 0454 <span style="color:#2980b9">wire</span> dwcr0_sel<span style="color:#3f8058">,</span> 0455 dwcr1_sel<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// DWCR selects</span> 0456 <span style="color:#2980b9">reg</span> dbg_bp_r<span style="color:#3f8058">;</span> 0457 <span style="color:#2980b9">reg</span> ex_freeze_q<span style="color:#3f8058">;</span> 0458 <span style="color:#27ae60">`ifdef OR1200_DU_HWBKPTS</span> 0459 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> match_cond0_ct<span style="color:#3f8058">;</span> 0460 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> match_cond1_ct<span style="color:#3f8058">;</span> 0461 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> match_cond2_ct<span style="color:#3f8058">;</span> 0462 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> match_cond3_ct<span style="color:#3f8058">;</span> 0463 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> match_cond4_ct<span style="color:#3f8058">;</span> 0464 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> match_cond5_ct<span style="color:#3f8058">;</span> 0465 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> match_cond6_ct<span style="color:#3f8058">;</span> 0466 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> match_cond7_ct<span style="color:#3f8058">;</span> 0467 <span style="color:#2980b9">reg</span> match_cond0_stb<span style="color:#3f8058">;</span> 0468 <span style="color:#2980b9">reg</span> match_cond1_stb<span style="color:#3f8058">;</span> 0469 <span style="color:#2980b9">reg</span> match_cond2_stb<span style="color:#3f8058">;</span> 0470 <span style="color:#2980b9">reg</span> match_cond3_stb<span style="color:#3f8058">;</span> 0471 <span style="color:#2980b9">reg</span> match_cond4_stb<span style="color:#3f8058">;</span> 0472 <span style="color:#2980b9">reg</span> match_cond5_stb<span style="color:#3f8058">;</span> 0473 <span style="color:#2980b9">reg</span> match_cond6_stb<span style="color:#3f8058">;</span> 0474 <span style="color:#2980b9">reg</span> match_cond7_stb<span style="color:#3f8058">;</span> 0475 <span style="color:#2980b9">reg</span> match0<span style="color:#3f8058">;</span> 0476 <span style="color:#2980b9">reg</span> match1<span style="color:#3f8058">;</span> 0477 <span style="color:#2980b9">reg</span> match2<span style="color:#3f8058">;</span> 0478 <span style="color:#2980b9">reg</span> match3<span style="color:#3f8058">;</span> 0479 <span style="color:#2980b9">reg</span> match4<span style="color:#3f8058">;</span> 0480 <span style="color:#2980b9">reg</span> match5<span style="color:#3f8058">;</span> 0481 <span style="color:#2980b9">reg</span> match6<span style="color:#3f8058">;</span> 0482 <span style="color:#2980b9">reg</span> match7<span style="color:#3f8058">;</span> 0483 <span style="color:#2980b9">reg</span> wpcntr0_match<span style="color:#3f8058">;</span> 0484 <span style="color:#2980b9">reg</span> wpcntr1_match<span style="color:#3f8058">;</span> 0485 <span style="color:#2980b9">reg</span> incr_wpcntr0<span style="color:#3f8058">;</span> 0486 <span style="color:#2980b9">reg</span> incr_wpcntr1<span style="color:#3f8058">;</span> 0487 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">10</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> wp<span style="color:#3f8058">;</span> 0488 <span style="color:#27ae60">`endif</span> 0489 <span style="color:#2980b9">wire</span> du_hwbkpt<span style="color:#3f8058">;</span> 0490 <span style="color:#2980b9">reg</span> du_hwbkpt_hold<span style="color:#3f8058">;</span> 0491 <span style="color:#27ae60">`ifdef OR1200_DU_READREGS</span> 0492 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> spr_dat_o<span style="color:#3f8058">;</span> 0493 <span style="color:#27ae60">`endif</span> 0494 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">13</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> except_stop<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// Exceptions that stop because of DSR</span> 0495 <span style="color:#27ae60">`ifdef OR1200_DU_TB_IMPLEMENTED</span> 0496 <span style="color:#2980b9">wire</span> tb_enw<span style="color:#3f8058">;</span> 0497 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> tb_wadr<span style="color:#3f8058">;</span> 0498 <span style="color:#2980b9">reg</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> tb_timstmp<span style="color:#3f8058">;</span> 0499 <span style="color:#27ae60">`endif</span> 0500 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> tbia_dat_o<span style="color:#3f8058">;</span> 0501 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> tbim_dat_o<span style="color:#3f8058">;</span> 0502 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> tbar_dat_o<span style="color:#3f8058">;</span> 0503 <span style="color:#2980b9">wire</span> <span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> tbts_dat_o<span style="color:#3f8058">;</span> 0504 0505 <span style="color:#7a7c7d">//</span> 0506 <span style="color:#7a7c7d">// DU registers address decoder</span> 0507 <span style="color:#7a7c7d">//</span> 0508 <span style="color:#27ae60">`ifdef OR1200_DU_DMR1</span> 0509 <span style="font-weight:bold">assign</span> dmr1_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DMR1</span><span style="color:#3f8058">));</span> 0510 <span style="color:#27ae60">`endif</span> 0511 <span style="color:#27ae60">`ifdef OR1200_DU_DMR2</span> 0512 <span style="font-weight:bold">assign</span> dmr2_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DMR2</span><span style="color:#3f8058">));</span> 0513 <span style="color:#27ae60">`endif</span> 0514 <span style="color:#27ae60">`ifdef OR1200_DU_DSR</span> 0515 <span style="font-weight:bold">assign</span> dsr_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DSR</span><span style="color:#3f8058">));</span> 0516 <span style="color:#27ae60">`endif</span> 0517 <span style="color:#27ae60">`ifdef OR1200_DU_DRR</span> 0518 <span style="font-weight:bold">assign</span> drr_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DRR</span><span style="color:#3f8058">));</span> 0519 <span style="color:#27ae60">`endif</span> 0520 <span style="color:#27ae60">`ifdef OR1200_DU_DVR0</span> 0521 <span style="font-weight:bold">assign</span> dvr0_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DVR0</span><span style="color:#3f8058">));</span> 0522 <span style="color:#27ae60">`endif</span> 0523 <span style="color:#27ae60">`ifdef OR1200_DU_DVR1</span> 0524 <span style="font-weight:bold">assign</span> dvr1_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DVR1</span><span style="color:#3f8058">));</span> 0525 <span style="color:#27ae60">`endif</span> 0526 <span style="color:#27ae60">`ifdef OR1200_DU_DVR2</span> 0527 <span style="font-weight:bold">assign</span> dvr2_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DVR2</span><span style="color:#3f8058">));</span> 0528 <span style="color:#27ae60">`endif</span> 0529 <span style="color:#27ae60">`ifdef OR1200_DU_DVR3</span> 0530 <span style="font-weight:bold">assign</span> dvr3_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DVR3</span><span style="color:#3f8058">));</span> 0531 <span style="color:#27ae60">`endif</span> 0532 <span style="color:#27ae60">`ifdef OR1200_DU_DVR4</span> 0533 <span style="font-weight:bold">assign</span> dvr4_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DVR4</span><span style="color:#3f8058">));</span> 0534 <span style="color:#27ae60">`endif</span> 0535 <span style="color:#27ae60">`ifdef OR1200_DU_DVR5</span> 0536 <span style="font-weight:bold">assign</span> dvr5_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DVR5</span><span style="color:#3f8058">));</span> 0537 <span style="color:#27ae60">`endif</span> 0538 <span style="color:#27ae60">`ifdef OR1200_DU_DVR6</span> 0539 <span style="font-weight:bold">assign</span> dvr6_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DVR6</span><span style="color:#3f8058">));</span> 0540 <span style="color:#27ae60">`endif</span> 0541 <span style="color:#27ae60">`ifdef OR1200_DU_DVR7</span> 0542 <span style="font-weight:bold">assign</span> dvr7_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DVR7</span><span style="color:#3f8058">));</span> 0543 <span style="color:#27ae60">`endif</span> 0544 <span style="color:#27ae60">`ifdef OR1200_DU_DCR0</span> 0545 <span style="font-weight:bold">assign</span> dcr0_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DCR0</span><span style="color:#3f8058">));</span> 0546 <span style="color:#27ae60">`endif</span> 0547 <span style="color:#27ae60">`ifdef OR1200_DU_DCR1</span> 0548 <span style="font-weight:bold">assign</span> dcr1_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DCR1</span><span style="color:#3f8058">));</span> 0549 <span style="color:#27ae60">`endif</span> 0550 <span style="color:#27ae60">`ifdef OR1200_DU_DCR2</span> 0551 <span style="font-weight:bold">assign</span> dcr2_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DCR2</span><span style="color:#3f8058">));</span> 0552 <span style="color:#27ae60">`endif</span> 0553 <span style="color:#27ae60">`ifdef OR1200_DU_DCR3</span> 0554 <span style="font-weight:bold">assign</span> dcr3_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DCR3</span><span style="color:#3f8058">));</span> 0555 <span style="color:#27ae60">`endif</span> 0556 <span style="color:#27ae60">`ifdef OR1200_DU_DCR4</span> 0557 <span style="font-weight:bold">assign</span> dcr4_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DCR4</span><span style="color:#3f8058">));</span> 0558 <span style="color:#27ae60">`endif</span> 0559 <span style="color:#27ae60">`ifdef OR1200_DU_DCR5</span> 0560 <span style="font-weight:bold">assign</span> dcr5_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DCR5</span><span style="color:#3f8058">));</span> 0561 <span style="color:#27ae60">`endif</span> 0562 <span style="color:#27ae60">`ifdef OR1200_DU_DCR6</span> 0563 <span style="font-weight:bold">assign</span> dcr6_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DCR6</span><span style="color:#3f8058">));</span> 0564 <span style="color:#27ae60">`endif</span> 0565 <span style="color:#27ae60">`ifdef OR1200_DU_DCR7</span> 0566 <span style="font-weight:bold">assign</span> dcr7_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DCR7</span><span style="color:#3f8058">));</span> 0567 <span style="color:#27ae60">`endif</span> 0568 <span style="color:#27ae60">`ifdef OR1200_DU_DWCR0</span> 0569 <span style="font-weight:bold">assign</span> dwcr0_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DWCR0</span><span style="color:#3f8058">));</span> 0570 <span style="color:#27ae60">`endif</span> 0571 <span style="color:#27ae60">`ifdef OR1200_DU_DWCR1</span> 0572 <span style="font-weight:bold">assign</span> dwcr1_sel <span style="color:#3f8058">=</span> <span style="color:#3f8058">(</span>spr_cs <span style="color:#3f8058">&&</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_DU_DWCR1</span><span style="color:#3f8058">));</span> 0573 <span style="color:#27ae60">`endif</span> 0574 0575 <span style="color:#7a7c7d">// Track previous ex_freeze to detect when signals are updated</span> 0576 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk<span style="color:#3f8058">)</span> 0577 ex_freeze_q <span style="color:#3f8058"><=</span> ex_freeze<span style="color:#3f8058">;</span> 0578 0579 <span style="color:#7a7c7d">//</span> 0580 <span style="color:#7a7c7d">// Decode started exception</span> 0581 <span style="color:#7a7c7d">//</span> 0582 <span style="color:#7a7c7d">// du_except_stop comes from or1200_except</span> 0583 <span style="color:#7a7c7d">// </span> 0584 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>du_except_stop <span style="color:#2980b9">or</span> ex_freeze_q<span style="color:#3f8058">)</span> <span style="font-weight:bold">begin</span> 0585 except_stop <span style="color:#3f8058">=</span> <span style="color:#f67400">14'b00_0000_0000_0000</span><span style="color:#3f8058">;</span> 0586 <span style="font-weight:bold">casez</span> <span style="color:#3f8058">(</span>du_except_stop<span style="color:#3f8058">)</span> 0587 <span style="color:#f67400">14'b1</span><span style="color:#3f8058">?</span>_<span style="color:#3f8058">????</span>_<span style="color:#3f8058">????</span>_<span style="color:#3f8058">????:</span> 0588 except_stop<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DRR_TTE</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> 0589 <span style="color:#f67400">14'b01_</span><span style="color:#3f8058">????</span>_<span style="color:#3f8058">????</span>_<span style="color:#3f8058">????:</span> <span style="font-weight:bold">begin</span> 0590 except_stop<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DRR_IE</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> 0591 <span style="font-weight:bold">end</span> 0592 <span style="color:#f67400">14'b00_1</span><span style="color:#3f8058">???</span>_<span style="color:#3f8058">????</span>_<span style="color:#3f8058">????:</span> <span style="font-weight:bold">begin</span> 0593 except_stop<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DRR_IME</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> 0594 <span style="font-weight:bold">end</span> 0595 <span style="color:#f67400">14'b00_01</span><span style="color:#3f8058">??</span>_<span style="color:#3f8058">????</span>_<span style="color:#3f8058">????:</span> 0596 except_stop<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DRR_IPFE</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> 0597 <span style="color:#f67400">14'b00_001</span><span style="color:#3f8058">?</span>_<span style="color:#3f8058">????</span>_<span style="color:#3f8058">????:</span> <span style="font-weight:bold">begin</span> 0598 except_stop<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DRR_BUSEE</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> 0599 <span style="font-weight:bold">end</span> 0600 <span style="color:#f67400">14'b00_0001_</span><span style="color:#3f8058">????</span>_<span style="color:#3f8058">????:</span> 0601 except_stop<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DRR_IIE</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> 0602 <span style="color:#f67400">14'b00_0000_1</span><span style="color:#3f8058">???</span>_<span style="color:#3f8058">????:</span> <span style="font-weight:bold">begin</span> 0603 except_stop<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DRR_AE</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> 0604 <span style="font-weight:bold">end</span> 0605 <span style="color:#f67400">14'b00_0000_01</span><span style="color:#3f8058">??</span>_<span style="color:#3f8058">????:</span> <span style="font-weight:bold">begin</span> 0606 except_stop<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DRR_DME</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> 0607 <span style="font-weight:bold">end</span> 0608 <span style="color:#f67400">14'b00_0000_001</span><span style="color:#3f8058">?</span>_<span style="color:#3f8058">????:</span> 0609 except_stop<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DRR_DPFE</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> 0610 <span style="color:#f67400">14'b00_0000_0001_</span><span style="color:#3f8058">????:</span> 0611 except_stop<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DRR_BUSEE</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> 0612 <span style="color:#f67400">14'b00_0000_0000_1</span><span style="color:#3f8058">???:</span> <span style="font-weight:bold">begin</span> 0613 except_stop<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DRR_RE</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> 0614 <span style="font-weight:bold">end</span> 0615 <span style="color:#f67400">14'b00_0000_0000_01</span><span style="color:#3f8058">??:</span> <span style="font-weight:bold">begin</span> 0616 except_stop<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DRR_TE</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span> <span style="color:#3f8058">&</span> <span style="color:#3f8058">~</span>ex_freeze_q<span style="color:#3f8058">;</span> 0617 <span style="font-weight:bold">end</span> 0618 <span style="color:#f67400">14'b00_0000_0000_001</span><span style="color:#3f8058">?:</span> <span style="font-weight:bold">begin</span> 0619 except_stop<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DRR_FPE</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> 0620 <span style="font-weight:bold">end</span> 0621 <span style="color:#f67400">14'b00_0000_0000_0001</span><span style="color:#3f8058">:</span> 0622 except_stop<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DRR_SCE</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span> <span style="color:#3f8058">&</span> <span style="color:#3f8058">~</span>ex_freeze_q<span style="color:#3f8058">;</span> 0623 <span style="font-weight:bold">default</span><span style="color:#3f8058">:</span> 0624 except_stop <span style="color:#3f8058">=</span> <span style="color:#f67400">14'b00_0000_0000_0000</span><span style="color:#3f8058">;</span> 0625 <span style="font-weight:bold">endcase</span> <span style="color:#7a7c7d">// casez (du_except_stop)</span> 0626 <span style="font-weight:bold">end</span> 0627 0628 <span style="color:#7a7c7d">//</span> 0629 <span style="color:#7a7c7d">// dbg_bp_o is registered</span> 0630 <span style="color:#7a7c7d">//</span> 0631 <span style="font-weight:bold">assign</span> dbg_bp_o <span style="color:#3f8058">=</span> dbg_bp_r<span style="color:#3f8058">;</span> 0632 0633 <span style="color:#7a7c7d">//</span> 0634 <span style="color:#7a7c7d">// Breakpoint activation register</span> 0635 <span style="color:#7a7c7d">//</span> 0636 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0637 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0638 dbg_bp_r <span style="color:#3f8058"><=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 0639 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(!</span>ex_freeze<span style="color:#3f8058">)</span> 0640 dbg_bp_r <span style="color:#3f8058"><=</span> <span style="color:#3f8058">|</span>except_stop 0641 <span style="color:#27ae60">`ifdef OR1200_DU_DMR1_ST</span> 0642 <span style="color:#3f8058">|</span> <span style="color:#3f8058">~((</span>ex_insn<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">26</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_OR32_NOP</span><span style="color:#3f8058">)</span> <span style="color:#3f8058">&</span> ex_insn<span style="color:#3f8058">[</span><span style="color:#f67400">16</span><span style="color:#3f8058">])</span> <span style="color:#3f8058">&</span> dmr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DMR1_ST</span><span style="color:#3f8058">]</span> 0643 <span style="color:#27ae60">`endif</span> 0644 <span style="color:#27ae60">`ifdef OR1200_DU_DMR1_BT</span> 0645 <span style="color:#3f8058">|</span> <span style="color:#3f8058">(</span>branch_op <span style="color:#3f8058">!=</span> <span style="color:#27ae60">`OR1200_BRANCHOP_NOP</span><span style="color:#3f8058">)</span> <span style="color:#3f8058">&</span> <span style="color:#3f8058">(</span>branch_op <span style="color:#3f8058">!=</span> <span style="color:#27ae60">`OR1200_BRANCHOP_RFE</span><span style="color:#3f8058">)</span> <span style="color:#3f8058">&</span> dmr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DMR1_BT</span><span style="color:#3f8058">]</span> 0646 <span style="color:#27ae60">`endif</span> 0647 <span style="color:#3f8058">;</span> 0648 <span style="font-weight:bold">else</span> 0649 dbg_bp_r <span style="color:#3f8058"><=</span> <span style="color:#3f8058">|</span>except_stop<span style="color:#3f8058">;</span> 0650 0651 <span style="color:#7a7c7d">//</span> 0652 <span style="color:#7a7c7d">// Write to DMR1</span> 0653 <span style="color:#7a7c7d">//</span> 0654 <span style="color:#27ae60">`ifdef OR1200_DU_DMR1</span> 0655 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0656 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0657 dmr1 <span style="color:#3f8058"><=</span> <span style="color:#f67400">25'h000_0000</span><span style="color:#3f8058">;</span> 0658 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dmr1_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0659 <span style="color:#27ae60">`ifdef OR1200_DU_HWBKPTS</span> 0660 dmr1 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">24</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0661 <span style="color:#27ae60">`else</span> 0662 dmr1 <span style="color:#3f8058"><=</span> <span style="color:#3f8058">{</span><span style="color:#f67400">1'b0</span><span style="color:#3f8058">,</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">23</span><span style="color:#3f8058">:</span><span style="color:#f67400">22</span><span style="color:#3f8058">],</span> <span style="color:#f67400">22'h00_0000</span><span style="color:#3f8058">};</span> 0663 <span style="color:#27ae60">`endif</span> 0664 <span style="color:#27ae60">`else</span> 0665 <span style="font-weight:bold">assign</span> dmr1 <span style="color:#3f8058">=</span> <span style="color:#f67400">25'h000_0000</span><span style="color:#3f8058">;</span> 0666 <span style="color:#27ae60">`endif</span> 0667 0668 <span style="color:#7a7c7d">//</span> 0669 <span style="color:#7a7c7d">// Write to DMR2</span> 0670 <span style="color:#7a7c7d">//</span> 0671 <span style="color:#27ae60">`ifdef OR1200_DU_DMR2</span> 0672 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0673 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0674 dmr2 <span style="color:#3f8058"><=</span> <span style="color:#f67400">24'h00_0000</span><span style="color:#3f8058">;</span> 0675 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dmr2_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0676 dmr2 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">23</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0677 <span style="color:#27ae60">`else</span> 0678 <span style="font-weight:bold">assign</span> dmr2 <span style="color:#3f8058">=</span> <span style="color:#f67400">24'h00_0000</span><span style="color:#3f8058">;</span> 0679 <span style="color:#27ae60">`endif</span> 0680 0681 <span style="color:#7a7c7d">//</span> 0682 <span style="color:#7a7c7d">// Write to DSR</span> 0683 <span style="color:#7a7c7d">//</span> 0684 <span style="color:#27ae60">`ifdef OR1200_DU_DSR</span> 0685 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0686 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0687 dsr <span style="color:#3f8058"><=</span> <span style="color:#3f8058">{</span><span style="color:#27ae60">`OR1200_DU_DSR_WIDTH</span><span style="color:#3f8058">{</span><span style="color:#f67400">1'b0</span><span style="color:#3f8058">}};</span> 0688 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dsr_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0689 dsr <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DSR_WIDTH</span><span style="color:#3f8058">-</span><span style="color:#f67400">1</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0690 <span style="color:#27ae60">`else</span> 0691 <span style="font-weight:bold">assign</span> dsr <span style="color:#3f8058">=</span> <span style="color:#3f8058">{</span><span style="color:#27ae60">`OR1200_DU_DSR_WIDTH</span><span style="color:#3f8058">{</span><span style="color:#f67400">1'b0</span><span style="color:#3f8058">}};</span> 0692 <span style="color:#27ae60">`endif</span> 0693 0694 <span style="color:#7a7c7d">//</span> 0695 <span style="color:#7a7c7d">// Write to DRR</span> 0696 <span style="color:#7a7c7d">//</span> 0697 <span style="color:#27ae60">`ifdef OR1200_DU_DRR</span> 0698 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0699 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0700 drr <span style="color:#3f8058"><=</span> <span style="color:#f67400">14'b0</span><span style="color:#3f8058">;</span> 0701 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>drr_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0702 drr <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">13</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0703 <span style="font-weight:bold">else</span> 0704 drr <span style="color:#3f8058"><=</span> drr <span style="color:#3f8058">|</span> except_stop<span style="color:#3f8058">;</span> 0705 <span style="color:#27ae60">`else</span> 0706 <span style="font-weight:bold">assign</span> drr <span style="color:#3f8058">=</span> <span style="color:#f67400">14'b0</span><span style="color:#3f8058">;</span> 0707 <span style="color:#27ae60">`endif</span> 0708 0709 <span style="color:#7a7c7d">//</span> 0710 <span style="color:#7a7c7d">// Write to DVR0</span> 0711 <span style="color:#7a7c7d">//</span> 0712 <span style="color:#27ae60">`ifdef OR1200_DU_DVR0</span> 0713 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0714 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0715 dvr0 <span style="color:#3f8058"><=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0716 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dvr0_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0717 dvr0 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0718 <span style="color:#27ae60">`else</span> 0719 <span style="font-weight:bold">assign</span> dvr0 <span style="color:#3f8058">=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0720 <span style="color:#27ae60">`endif</span> 0721 0722 <span style="color:#7a7c7d">//</span> 0723 <span style="color:#7a7c7d">// Write to DVR1</span> 0724 <span style="color:#7a7c7d">//</span> 0725 <span style="color:#27ae60">`ifdef OR1200_DU_DVR1</span> 0726 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0727 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0728 dvr1 <span style="color:#3f8058"><=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0729 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dvr1_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0730 dvr1 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0731 <span style="color:#27ae60">`else</span> 0732 <span style="font-weight:bold">assign</span> dvr1 <span style="color:#3f8058">=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0733 <span style="color:#27ae60">`endif</span> 0734 0735 <span style="color:#7a7c7d">//</span> 0736 <span style="color:#7a7c7d">// Write to DVR2</span> 0737 <span style="color:#7a7c7d">//</span> 0738 <span style="color:#27ae60">`ifdef OR1200_DU_DVR2</span> 0739 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0740 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0741 dvr2 <span style="color:#3f8058"><=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0742 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dvr2_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0743 dvr2 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0744 <span style="color:#27ae60">`else</span> 0745 <span style="font-weight:bold">assign</span> dvr2 <span style="color:#3f8058">=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0746 <span style="color:#27ae60">`endif</span> 0747 0748 <span style="color:#7a7c7d">//</span> 0749 <span style="color:#7a7c7d">// Write to DVR3</span> 0750 <span style="color:#7a7c7d">//</span> 0751 <span style="color:#27ae60">`ifdef OR1200_DU_DVR3</span> 0752 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0753 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0754 dvr3 <span style="color:#3f8058"><=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0755 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dvr3_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0756 dvr3 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0757 <span style="color:#27ae60">`else</span> 0758 <span style="font-weight:bold">assign</span> dvr3 <span style="color:#3f8058">=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0759 <span style="color:#27ae60">`endif</span> 0760 0761 <span style="color:#7a7c7d">//</span> 0762 <span style="color:#7a7c7d">// Write to DVR4</span> 0763 <span style="color:#7a7c7d">//</span> 0764 <span style="color:#27ae60">`ifdef OR1200_DU_DVR4</span> 0765 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0766 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0767 dvr4 <span style="color:#3f8058"><=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0768 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dvr4_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0769 dvr4 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0770 <span style="color:#27ae60">`else</span> 0771 <span style="font-weight:bold">assign</span> dvr4 <span style="color:#3f8058">=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0772 <span style="color:#27ae60">`endif</span> 0773 0774 <span style="color:#7a7c7d">//</span> 0775 <span style="color:#7a7c7d">// Write to DVR5</span> 0776 <span style="color:#7a7c7d">//</span> 0777 <span style="color:#27ae60">`ifdef OR1200_DU_DVR5</span> 0778 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0779 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0780 dvr5 <span style="color:#3f8058"><=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0781 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dvr5_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0782 dvr5 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0783 <span style="color:#27ae60">`else</span> 0784 <span style="font-weight:bold">assign</span> dvr5 <span style="color:#3f8058">=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0785 <span style="color:#27ae60">`endif</span> 0786 0787 <span style="color:#7a7c7d">//</span> 0788 <span style="color:#7a7c7d">// Write to DVR6</span> 0789 <span style="color:#7a7c7d">//</span> 0790 <span style="color:#27ae60">`ifdef OR1200_DU_DVR6</span> 0791 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0792 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0793 dvr6 <span style="color:#3f8058"><=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0794 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dvr6_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0795 dvr6 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0796 <span style="color:#27ae60">`else</span> 0797 <span style="font-weight:bold">assign</span> dvr6 <span style="color:#3f8058">=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0798 <span style="color:#27ae60">`endif</span> 0799 0800 <span style="color:#7a7c7d">//</span> 0801 <span style="color:#7a7c7d">// Write to DVR7</span> 0802 <span style="color:#7a7c7d">//</span> 0803 <span style="color:#27ae60">`ifdef OR1200_DU_DVR7</span> 0804 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0805 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0806 dvr7 <span style="color:#3f8058"><=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0807 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dvr7_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0808 dvr7 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0809 <span style="color:#27ae60">`else</span> 0810 <span style="font-weight:bold">assign</span> dvr7 <span style="color:#3f8058">=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0811 <span style="color:#27ae60">`endif</span> 0812 0813 <span style="color:#7a7c7d">//</span> 0814 <span style="color:#7a7c7d">// Write to DCR0</span> 0815 <span style="color:#7a7c7d">//</span> 0816 <span style="color:#27ae60">`ifdef OR1200_DU_DCR0</span> 0817 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0818 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0819 dcr0 <span style="color:#3f8058"><=</span> <span style="color:#f67400">8'h00</span><span style="color:#3f8058">;</span> 0820 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dcr0_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0821 dcr0 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0822 <span style="color:#27ae60">`else</span> 0823 <span style="font-weight:bold">assign</span> dcr0 <span style="color:#3f8058">=</span> <span style="color:#f67400">8'h00</span><span style="color:#3f8058">;</span> 0824 <span style="color:#27ae60">`endif</span> 0825 0826 <span style="color:#7a7c7d">//</span> 0827 <span style="color:#7a7c7d">// Write to DCR1</span> 0828 <span style="color:#7a7c7d">//</span> 0829 <span style="color:#27ae60">`ifdef OR1200_DU_DCR1</span> 0830 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0831 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0832 dcr1 <span style="color:#3f8058"><=</span> <span style="color:#f67400">8'h00</span><span style="color:#3f8058">;</span> 0833 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dcr1_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0834 dcr1 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0835 <span style="color:#27ae60">`else</span> 0836 <span style="font-weight:bold">assign</span> dcr1 <span style="color:#3f8058">=</span> <span style="color:#f67400">8'h00</span><span style="color:#3f8058">;</span> 0837 <span style="color:#27ae60">`endif</span> 0838 0839 <span style="color:#7a7c7d">//</span> 0840 <span style="color:#7a7c7d">// Write to DCR2</span> 0841 <span style="color:#7a7c7d">//</span> 0842 <span style="color:#27ae60">`ifdef OR1200_DU_DCR2</span> 0843 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0844 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0845 dcr2 <span style="color:#3f8058"><=</span> <span style="color:#f67400">8'h00</span><span style="color:#3f8058">;</span> 0846 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dcr2_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0847 dcr2 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0848 <span style="color:#27ae60">`else</span> 0849 <span style="font-weight:bold">assign</span> dcr2 <span style="color:#3f8058">=</span> <span style="color:#f67400">8'h00</span><span style="color:#3f8058">;</span> 0850 <span style="color:#27ae60">`endif</span> 0851 0852 <span style="color:#7a7c7d">//</span> 0853 <span style="color:#7a7c7d">// Write to DCR3</span> 0854 <span style="color:#7a7c7d">//</span> 0855 <span style="color:#27ae60">`ifdef OR1200_DU_DCR3</span> 0856 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0857 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0858 dcr3 <span style="color:#3f8058"><=</span> <span style="color:#f67400">8'h00</span><span style="color:#3f8058">;</span> 0859 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dcr3_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0860 dcr3 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0861 <span style="color:#27ae60">`else</span> 0862 <span style="font-weight:bold">assign</span> dcr3 <span style="color:#3f8058">=</span> <span style="color:#f67400">8'h00</span><span style="color:#3f8058">;</span> 0863 <span style="color:#27ae60">`endif</span> 0864 0865 <span style="color:#7a7c7d">//</span> 0866 <span style="color:#7a7c7d">// Write to DCR4</span> 0867 <span style="color:#7a7c7d">//</span> 0868 <span style="color:#27ae60">`ifdef OR1200_DU_DCR4</span> 0869 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0870 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0871 dcr4 <span style="color:#3f8058"><=</span> <span style="color:#f67400">8'h00</span><span style="color:#3f8058">;</span> 0872 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dcr4_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0873 dcr4 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0874 <span style="color:#27ae60">`else</span> 0875 <span style="font-weight:bold">assign</span> dcr4 <span style="color:#3f8058">=</span> <span style="color:#f67400">8'h00</span><span style="color:#3f8058">;</span> 0876 <span style="color:#27ae60">`endif</span> 0877 0878 <span style="color:#7a7c7d">//</span> 0879 <span style="color:#7a7c7d">// Write to DCR5</span> 0880 <span style="color:#7a7c7d">//</span> 0881 <span style="color:#27ae60">`ifdef OR1200_DU_DCR5</span> 0882 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0883 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0884 dcr5 <span style="color:#3f8058"><=</span> <span style="color:#f67400">8'h00</span><span style="color:#3f8058">;</span> 0885 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dcr5_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0886 dcr5 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0887 <span style="color:#27ae60">`else</span> 0888 <span style="font-weight:bold">assign</span> dcr5 <span style="color:#3f8058">=</span> <span style="color:#f67400">8'h00</span><span style="color:#3f8058">;</span> 0889 <span style="color:#27ae60">`endif</span> 0890 0891 <span style="color:#7a7c7d">//</span> 0892 <span style="color:#7a7c7d">// Write to DCR6</span> 0893 <span style="color:#7a7c7d">//</span> 0894 <span style="color:#27ae60">`ifdef OR1200_DU_DCR6</span> 0895 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0896 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0897 dcr6 <span style="color:#3f8058"><=</span> <span style="color:#f67400">8'h00</span><span style="color:#3f8058">;</span> 0898 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dcr6_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0899 dcr6 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0900 <span style="color:#27ae60">`else</span> 0901 <span style="font-weight:bold">assign</span> dcr6 <span style="color:#3f8058">=</span> <span style="color:#f67400">8'h00</span><span style="color:#3f8058">;</span> 0902 <span style="color:#27ae60">`endif</span> 0903 0904 <span style="color:#7a7c7d">//</span> 0905 <span style="color:#7a7c7d">// Write to DCR7</span> 0906 <span style="color:#7a7c7d">//</span> 0907 <span style="color:#27ae60">`ifdef OR1200_DU_DCR7</span> 0908 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0909 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0910 dcr7 <span style="color:#3f8058"><=</span> <span style="color:#f67400">8'h00</span><span style="color:#3f8058">;</span> 0911 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dcr7_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0912 dcr7 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0913 <span style="color:#27ae60">`else</span> 0914 <span style="font-weight:bold">assign</span> dcr7 <span style="color:#3f8058">=</span> <span style="color:#f67400">8'h00</span><span style="color:#3f8058">;</span> 0915 <span style="color:#27ae60">`endif</span> 0916 0917 <span style="color:#7a7c7d">//</span> 0918 <span style="color:#7a7c7d">// Write to DWCR0</span> 0919 <span style="color:#7a7c7d">//</span> 0920 <span style="color:#27ae60">`ifdef OR1200_DU_DWCR0</span> 0921 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0922 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0923 dwcr0 <span style="color:#3f8058"><=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0924 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dwcr0_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0925 dwcr0 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0926 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>incr_wpcntr0<span style="color:#3f8058">)</span> 0927 dwcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DWCR_COUNT</span><span style="color:#3f8058">]</span> <span style="color:#3f8058"><=</span> dwcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DWCR_COUNT</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">+</span> <span style="color:#f67400">16'h0001</span><span style="color:#3f8058">;</span> 0928 <span style="color:#27ae60">`else</span> 0929 <span style="font-weight:bold">assign</span> dwcr0 <span style="color:#3f8058">=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0930 <span style="color:#27ae60">`endif</span> 0931 0932 <span style="color:#7a7c7d">//</span> 0933 <span style="color:#7a7c7d">// Write to DWCR1</span> 0934 <span style="color:#7a7c7d">//</span> 0935 <span style="color:#27ae60">`ifdef OR1200_DU_DWCR1</span> 0936 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 0937 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 0938 dwcr1 <span style="color:#3f8058"><=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0939 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dwcr1_sel <span style="color:#3f8058">&&</span> spr_write<span style="color:#3f8058">)</span> 0940 dwcr1 <span style="color:#3f8058"><=</span> spr_dat_i<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 0941 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>incr_wpcntr1<span style="color:#3f8058">)</span> 0942 dwcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DWCR_COUNT</span><span style="color:#3f8058">]</span> <span style="color:#3f8058"><=</span> dwcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DWCR_COUNT</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">+</span> <span style="color:#f67400">16'h0001</span><span style="color:#3f8058">;</span> 0943 <span style="color:#27ae60">`else</span> 0944 <span style="font-weight:bold">assign</span> dwcr1 <span style="color:#3f8058">=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 0945 <span style="color:#27ae60">`endif</span> 0946 0947 <span style="color:#7a7c7d">//</span> 0948 <span style="color:#7a7c7d">// Read DU registers</span> 0949 <span style="color:#7a7c7d">//</span> 0950 <span style="color:#27ae60">`ifdef OR1200_DU_READREGS</span> 0951 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>spr_addr <span style="color:#2980b9">or</span> dsr <span style="color:#2980b9">or</span> drr <span style="color:#2980b9">or</span> dmr1 <span style="color:#2980b9">or</span> dmr2 0952 <span style="color:#2980b9">or</span> dvr0 <span style="color:#2980b9">or</span> dvr1 <span style="color:#2980b9">or</span> dvr2 <span style="color:#2980b9">or</span> dvr3 <span style="color:#2980b9">or</span> dvr4 0953 <span style="color:#2980b9">or</span> dvr5 <span style="color:#2980b9">or</span> dvr6 <span style="color:#2980b9">or</span> dvr7 0954 <span style="color:#2980b9">or</span> dcr0 <span style="color:#2980b9">or</span> dcr1 <span style="color:#2980b9">or</span> dcr2 <span style="color:#2980b9">or</span> dcr3 <span style="color:#2980b9">or</span> dcr4 0955 <span style="color:#2980b9">or</span> dcr5 <span style="color:#2980b9">or</span> dcr6 <span style="color:#2980b9">or</span> dcr7 0956 <span style="color:#2980b9">or</span> dwcr0 <span style="color:#2980b9">or</span> dwcr1 0957 <span style="color:#27ae60">`ifdef OR1200_DU_TB_IMPLEMENTED</span> 0958 <span style="color:#2980b9">or</span> tb_wadr <span style="color:#2980b9">or</span> tbia_dat_o <span style="color:#2980b9">or</span> tbim_dat_o 0959 <span style="color:#2980b9">or</span> tbar_dat_o <span style="color:#2980b9">or</span> tbts_dat_o 0960 <span style="color:#27ae60">`endif</span> 0961 <span style="color:#3f8058">)</span> 0962 <span style="font-weight:bold">casez</span> <span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DUOFS_BITS</span><span style="color:#3f8058">])</span> <span style="color:#7a7c7d">// synopsys parallel_case</span> 0963 <span style="color:#27ae60">`ifdef OR1200_DU_DVR0</span> 0964 <span style="color:#27ae60">`OR1200_DU_DVR0</span><span style="color:#3f8058">:</span> 0965 spr_dat_o <span style="color:#3f8058">=</span> dvr0<span style="color:#3f8058">;</span> 0966 <span style="color:#27ae60">`endif</span> 0967 <span style="color:#27ae60">`ifdef OR1200_DU_DVR1</span> 0968 <span style="color:#27ae60">`OR1200_DU_DVR1</span><span style="color:#3f8058">:</span> 0969 spr_dat_o <span style="color:#3f8058">=</span> dvr1<span style="color:#3f8058">;</span> 0970 <span style="color:#27ae60">`endif</span> 0971 <span style="color:#27ae60">`ifdef OR1200_DU_DVR2</span> 0972 <span style="color:#27ae60">`OR1200_DU_DVR2</span><span style="color:#3f8058">:</span> 0973 spr_dat_o <span style="color:#3f8058">=</span> dvr2<span style="color:#3f8058">;</span> 0974 <span style="color:#27ae60">`endif</span> 0975 <span style="color:#27ae60">`ifdef OR1200_DU_DVR3</span> 0976 <span style="color:#27ae60">`OR1200_DU_DVR3</span><span style="color:#3f8058">:</span> 0977 spr_dat_o <span style="color:#3f8058">=</span> dvr3<span style="color:#3f8058">;</span> 0978 <span style="color:#27ae60">`endif</span> 0979 <span style="color:#27ae60">`ifdef OR1200_DU_DVR4</span> 0980 <span style="color:#27ae60">`OR1200_DU_DVR4</span><span style="color:#3f8058">:</span> 0981 spr_dat_o <span style="color:#3f8058">=</span> dvr4<span style="color:#3f8058">;</span> 0982 <span style="color:#27ae60">`endif</span> 0983 <span style="color:#27ae60">`ifdef OR1200_DU_DVR5</span> 0984 <span style="color:#27ae60">`OR1200_DU_DVR5</span><span style="color:#3f8058">:</span> 0985 spr_dat_o <span style="color:#3f8058">=</span> dvr5<span style="color:#3f8058">;</span> 0986 <span style="color:#27ae60">`endif</span> 0987 <span style="color:#27ae60">`ifdef OR1200_DU_DVR6</span> 0988 <span style="color:#27ae60">`OR1200_DU_DVR6</span><span style="color:#3f8058">:</span> 0989 spr_dat_o <span style="color:#3f8058">=</span> dvr6<span style="color:#3f8058">;</span> 0990 <span style="color:#27ae60">`endif</span> 0991 <span style="color:#27ae60">`ifdef OR1200_DU_DVR7</span> 0992 <span style="color:#27ae60">`OR1200_DU_DVR7</span><span style="color:#3f8058">:</span> 0993 spr_dat_o <span style="color:#3f8058">=</span> dvr7<span style="color:#3f8058">;</span> 0994 <span style="color:#27ae60">`endif</span> 0995 <span style="color:#27ae60">`ifdef OR1200_DU_DCR0</span> 0996 <span style="color:#27ae60">`OR1200_DU_DCR0</span><span style="color:#3f8058">:</span> 0997 spr_dat_o <span style="color:#3f8058">=</span> <span style="color:#3f8058">{</span><span style="color:#f67400">24'h00_0000</span><span style="color:#3f8058">,</span> dcr0<span style="color:#3f8058">};</span> 0998 <span style="color:#27ae60">`endif</span> 0999 <span style="color:#27ae60">`ifdef OR1200_DU_DCR1</span> 1000 <span style="color:#27ae60">`OR1200_DU_DCR1</span><span style="color:#3f8058">:</span> 1001 spr_dat_o <span style="color:#3f8058">=</span> <span style="color:#3f8058">{</span><span style="color:#f67400">24'h00_0000</span><span style="color:#3f8058">,</span> dcr1<span style="color:#3f8058">};</span> 1002 <span style="color:#27ae60">`endif</span> 1003 <span style="color:#27ae60">`ifdef OR1200_DU_DCR2</span> 1004 <span style="color:#27ae60">`OR1200_DU_DCR2</span><span style="color:#3f8058">:</span> 1005 spr_dat_o <span style="color:#3f8058">=</span> <span style="color:#3f8058">{</span><span style="color:#f67400">24'h00_0000</span><span style="color:#3f8058">,</span> dcr2<span style="color:#3f8058">};</span> 1006 <span style="color:#27ae60">`endif</span> 1007 <span style="color:#27ae60">`ifdef OR1200_DU_DCR3</span> 1008 <span style="color:#27ae60">`OR1200_DU_DCR3</span><span style="color:#3f8058">:</span> 1009 spr_dat_o <span style="color:#3f8058">=</span> <span style="color:#3f8058">{</span><span style="color:#f67400">24'h00_0000</span><span style="color:#3f8058">,</span> dcr3<span style="color:#3f8058">};</span> 1010 <span style="color:#27ae60">`endif</span> 1011 <span style="color:#27ae60">`ifdef OR1200_DU_DCR4</span> 1012 <span style="color:#27ae60">`OR1200_DU_DCR4</span><span style="color:#3f8058">:</span> 1013 spr_dat_o <span style="color:#3f8058">=</span> <span style="color:#3f8058">{</span><span style="color:#f67400">24'h00_0000</span><span style="color:#3f8058">,</span> dcr4<span style="color:#3f8058">};</span> 1014 <span style="color:#27ae60">`endif</span> 1015 <span style="color:#27ae60">`ifdef OR1200_DU_DCR5</span> 1016 <span style="color:#27ae60">`OR1200_DU_DCR5</span><span style="color:#3f8058">:</span> 1017 spr_dat_o <span style="color:#3f8058">=</span> <span style="color:#3f8058">{</span><span style="color:#f67400">24'h00_0000</span><span style="color:#3f8058">,</span> dcr5<span style="color:#3f8058">};</span> 1018 <span style="color:#27ae60">`endif</span> 1019 <span style="color:#27ae60">`ifdef OR1200_DU_DCR6</span> 1020 <span style="color:#27ae60">`OR1200_DU_DCR6</span><span style="color:#3f8058">:</span> 1021 spr_dat_o <span style="color:#3f8058">=</span> <span style="color:#3f8058">{</span><span style="color:#f67400">24'h00_0000</span><span style="color:#3f8058">,</span> dcr6<span style="color:#3f8058">};</span> 1022 <span style="color:#27ae60">`endif</span> 1023 <span style="color:#27ae60">`ifdef OR1200_DU_DCR7</span> 1024 <span style="color:#27ae60">`OR1200_DU_DCR7</span><span style="color:#3f8058">:</span> 1025 spr_dat_o <span style="color:#3f8058">=</span> <span style="color:#3f8058">{</span><span style="color:#f67400">24'h00_0000</span><span style="color:#3f8058">,</span> dcr7<span style="color:#3f8058">};</span> 1026 <span style="color:#27ae60">`endif</span> 1027 <span style="color:#27ae60">`ifdef OR1200_DU_DMR1</span> 1028 <span style="color:#27ae60">`OR1200_DU_DMR1</span><span style="color:#3f8058">:</span> 1029 spr_dat_o <span style="color:#3f8058">=</span> <span style="color:#3f8058">{</span><span style="color:#f67400">7'h00</span><span style="color:#3f8058">,</span> dmr1<span style="color:#3f8058">};</span> 1030 <span style="color:#27ae60">`endif</span> 1031 <span style="color:#27ae60">`ifdef OR1200_DU_DMR2</span> 1032 <span style="color:#27ae60">`OR1200_DU_DMR2</span><span style="color:#3f8058">:</span> 1033 spr_dat_o <span style="color:#3f8058">=</span> <span style="color:#3f8058">{</span><span style="color:#f67400">8'h00</span><span style="color:#3f8058">,</span> dmr2<span style="color:#3f8058">};</span> 1034 <span style="color:#27ae60">`endif</span> 1035 <span style="color:#27ae60">`ifdef OR1200_DU_DWCR0</span> 1036 <span style="color:#27ae60">`OR1200_DU_DWCR0</span><span style="color:#3f8058">:</span> 1037 spr_dat_o <span style="color:#3f8058">=</span> dwcr0<span style="color:#3f8058">;</span> 1038 <span style="color:#27ae60">`endif</span> 1039 <span style="color:#27ae60">`ifdef OR1200_DU_DWCR1</span> 1040 <span style="color:#27ae60">`OR1200_DU_DWCR1</span><span style="color:#3f8058">:</span> 1041 spr_dat_o <span style="color:#3f8058">=</span> dwcr1<span style="color:#3f8058">;</span> 1042 <span style="color:#27ae60">`endif</span> 1043 <span style="color:#27ae60">`ifdef OR1200_DU_DSR</span> 1044 <span style="color:#27ae60">`OR1200_DU_DSR</span><span style="color:#3f8058">:</span> 1045 spr_dat_o <span style="color:#3f8058">=</span> <span style="color:#3f8058">{</span><span style="color:#f67400">18'b0</span><span style="color:#3f8058">,</span> dsr<span style="color:#3f8058">};</span> 1046 <span style="color:#27ae60">`endif</span> 1047 <span style="color:#27ae60">`ifdef OR1200_DU_DRR</span> 1048 <span style="color:#27ae60">`OR1200_DU_DRR</span><span style="color:#3f8058">:</span> 1049 spr_dat_o <span style="color:#3f8058">=</span> <span style="color:#3f8058">{</span><span style="color:#f67400">18'b0</span><span style="color:#3f8058">,</span> drr<span style="color:#3f8058">};</span> 1050 <span style="color:#27ae60">`endif</span> 1051 <span style="color:#27ae60">`ifdef OR1200_DU_TB_IMPLEMENTED</span> 1052 <span style="color:#27ae60">`OR1200_DU_TBADR</span><span style="color:#3f8058">:</span> 1053 spr_dat_o <span style="color:#3f8058">=</span> <span style="color:#3f8058">{</span><span style="color:#f67400">24'h000000</span><span style="color:#3f8058">,</span> tb_wadr<span style="color:#3f8058">};</span> 1054 <span style="color:#27ae60">`OR1200_DU_TBIA</span><span style="color:#3f8058">:</span> 1055 spr_dat_o <span style="color:#3f8058">=</span> tbia_dat_o<span style="color:#3f8058">;</span> 1056 <span style="color:#27ae60">`OR1200_DU_TBIM</span><span style="color:#3f8058">:</span> 1057 spr_dat_o <span style="color:#3f8058">=</span> tbim_dat_o<span style="color:#3f8058">;</span> 1058 <span style="color:#27ae60">`OR1200_DU_TBAR</span><span style="color:#3f8058">:</span> 1059 spr_dat_o <span style="color:#3f8058">=</span> tbar_dat_o<span style="color:#3f8058">;</span> 1060 <span style="color:#27ae60">`OR1200_DU_TBTS</span><span style="color:#3f8058">:</span> 1061 spr_dat_o <span style="color:#3f8058">=</span> tbts_dat_o<span style="color:#3f8058">;</span> 1062 <span style="color:#27ae60">`endif</span> 1063 <span style="font-weight:bold">default</span><span style="color:#3f8058">:</span> 1064 spr_dat_o <span style="color:#3f8058">=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 1065 <span style="font-weight:bold">endcase</span> 1066 <span style="color:#27ae60">`endif</span> 1067 1068 <span style="color:#7a7c7d">//</span> 1069 <span style="color:#7a7c7d">// DSR alias</span> 1070 <span style="color:#7a7c7d">//</span> 1071 <span style="font-weight:bold">assign</span> du_dsr <span style="color:#3f8058">=</span> dsr<span style="color:#3f8058">;</span> 1072 1073 <span style="color:#27ae60">`ifdef OR1200_DU_HWBKPTS</span> 1074 1075 <span style="color:#7a7c7d">//</span> 1076 <span style="color:#7a7c7d">// Compare To What (Match Condition 0)</span> 1077 <span style="color:#7a7c7d">//</span> 1078 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dcr0 <span style="color:#2980b9">or</span> id_pc <span style="color:#2980b9">or</span> dcpu_adr_i <span style="color:#2980b9">or</span> dcpu_dat_dc 1079 <span style="color:#2980b9">or</span> dcpu_dat_lsu <span style="color:#2980b9">or</span> dcpu_we_i<span style="color:#3f8058">)</span> 1080 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CT</span><span style="color:#3f8058">])</span> <span style="color:#7a7c7d">// synopsys parallel_case</span> 1081 <span style="color:#f67400">3'b001</span><span style="color:#3f8058">:</span> match_cond0_ct <span style="color:#3f8058">=</span> id_pc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// insn fetch EA</span> 1082 <span style="color:#f67400">3'b010</span><span style="color:#3f8058">:</span> match_cond0_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load EA</span> 1083 <span style="color:#f67400">3'b011</span><span style="color:#3f8058">:</span> match_cond0_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// store EA</span> 1084 <span style="color:#f67400">3'b100</span><span style="color:#3f8058">:</span> match_cond0_ct <span style="color:#3f8058">=</span> dcpu_dat_dc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load data</span> 1085 <span style="color:#f67400">3'b101</span><span style="color:#3f8058">:</span> match_cond0_ct <span style="color:#3f8058">=</span> dcpu_dat_lsu<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// store data</span> 1086 <span style="color:#f67400">3'b110</span><span style="color:#3f8058">:</span> match_cond0_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load/store EA</span> 1087 <span style="font-weight:bold">default</span><span style="color:#3f8058">:</span>match_cond0_ct <span style="color:#3f8058">=</span> dcpu_we_i <span style="color:#3f8058">?</span> dcpu_dat_lsu <span style="color:#3f8058">:</span> dcpu_dat_dc<span style="color:#3f8058">;</span> 1088 <span style="font-weight:bold">endcase</span> 1089 1090 <span style="color:#7a7c7d">//</span> 1091 <span style="color:#7a7c7d">// When To Compare (Match Condition 0)</span> 1092 <span style="color:#7a7c7d">//</span> 1093 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dcr0 <span style="color:#2980b9">or</span> dcpu_cycstb_i<span style="color:#3f8058">)</span> 1094 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CT</span><span style="color:#3f8058">])</span> <span style="color:#7a7c7d">// synopsys parallel_case</span> 1095 <span style="color:#f67400">3'b000</span><span style="color:#3f8058">:</span> match_cond0_stb <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> <span style="color:#7a7c7d">//comparison disabled</span> 1096 <span style="color:#f67400">3'b001</span><span style="color:#3f8058">:</span> match_cond0_stb <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// insn fetch EA</span> 1097 <span style="font-weight:bold">default</span><span style="color:#3f8058">:</span>match_cond0_stb <span style="color:#3f8058">=</span> dcpu_cycstb_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// any load/store</span> 1098 <span style="font-weight:bold">endcase</span> 1099 1100 <span style="color:#7a7c7d">//</span> 1101 <span style="color:#7a7c7d">// Match Condition 0</span> 1102 <span style="color:#7a7c7d">//</span> 1103 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>match_cond0_stb <span style="color:#2980b9">or</span> dcr0 <span style="color:#2980b9">or</span> dvr0 <span style="color:#2980b9">or</span> match_cond0_ct<span style="color:#3f8058">)</span> 1104 <span style="font-weight:bold">casex</span> <span style="color:#3f8058">({</span>match_cond0_stb<span style="color:#3f8058">,</span> dcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CC</span><span style="color:#3f8058">]})</span> 1105 <span style="color:#f67400">4'b0_xxx</span><span style="color:#3f8058">,</span> 1106 <span style="color:#f67400">4'b1_000</span><span style="color:#3f8058">,</span> 1107 <span style="color:#f67400">4'b1_111</span><span style="color:#3f8058">:</span> match0 <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1108 <span style="color:#f67400">4'b1_001</span><span style="color:#3f8058">:</span> match0 <span style="color:#3f8058">=</span> 1109 <span style="color:#3f8058">({(</span>match_cond0_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond0_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">==</span> 1110 <span style="color:#3f8058">{(</span>dvr0<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr0<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1111 <span style="color:#f67400">4'b1_010</span><span style="color:#3f8058">:</span> match0 <span style="color:#3f8058">=</span> 1112 <span style="color:#3f8058">({(</span>match_cond0_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond0_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058"><</span> 1113 <span style="color:#3f8058">{(</span>dvr0<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr0<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1114 <span style="color:#f67400">4'b1_011</span><span style="color:#3f8058">:</span> match0 <span style="color:#3f8058">=</span> 1115 <span style="color:#3f8058">({(</span>match_cond0_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond0_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058"><=</span> 1116 <span style="color:#3f8058">{(</span>dvr0<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr0<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1117 <span style="color:#f67400">4'b1_100</span><span style="color:#3f8058">:</span> match0 <span style="color:#3f8058">=</span> 1118 <span style="color:#3f8058">({(</span>match_cond0_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond0_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">></span> 1119 <span style="color:#3f8058">{(</span>dvr0<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr0<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1120 <span style="color:#f67400">4'b1_101</span><span style="color:#3f8058">:</span> match0 <span style="color:#3f8058">=</span> 1121 <span style="color:#3f8058">({(</span>match_cond0_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond0_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">>=</span> 1122 <span style="color:#3f8058">{(</span>dvr0<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr0<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1123 <span style="color:#f67400">4'b1_110</span><span style="color:#3f8058">:</span> match0 <span style="color:#3f8058">=</span> 1124 <span style="color:#3f8058">({(</span>match_cond0_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond0_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">!=</span> 1125 <span style="color:#3f8058">{(</span>dvr0<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr0<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1126 <span style="font-weight:bold">endcase</span> 1127 1128 <span style="color:#7a7c7d">//</span> 1129 <span style="color:#7a7c7d">// Watchpoint 0</span> 1130 <span style="color:#7a7c7d">//</span> 1131 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dmr1 <span style="color:#2980b9">or</span> match0<span style="color:#3f8058">)</span> 1132 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dmr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DMR1_CW0</span><span style="color:#3f8058">])</span> 1133 <span style="color:#f67400">2'b00</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match0<span style="color:#3f8058">;</span> 1134 <span style="color:#f67400">2'b01</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match0<span style="color:#3f8058">;</span> 1135 <span style="color:#f67400">2'b10</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match0<span style="color:#3f8058">;</span> 1136 <span style="color:#f67400">2'b11</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">0</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1137 <span style="font-weight:bold">endcase</span> 1138 1139 <span style="color:#7a7c7d">//</span> 1140 <span style="color:#7a7c7d">// Compare To What (Match Condition 1)</span> 1141 <span style="color:#7a7c7d">//</span> 1142 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dcr1 <span style="color:#2980b9">or</span> id_pc <span style="color:#2980b9">or</span> dcpu_adr_i <span style="color:#2980b9">or</span> dcpu_dat_dc 1143 <span style="color:#2980b9">or</span> dcpu_dat_lsu <span style="color:#2980b9">or</span> dcpu_we_i<span style="color:#3f8058">)</span> 1144 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CT</span><span style="color:#3f8058">])</span> <span style="color:#7a7c7d">// synopsys parallel_case</span> 1145 <span style="color:#f67400">3'b001</span><span style="color:#3f8058">:</span> match_cond1_ct <span style="color:#3f8058">=</span> id_pc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// insn fetch EA</span> 1146 <span style="color:#f67400">3'b010</span><span style="color:#3f8058">:</span> match_cond1_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load EA</span> 1147 <span style="color:#f67400">3'b011</span><span style="color:#3f8058">:</span> match_cond1_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// store EA</span> 1148 <span style="color:#f67400">3'b100</span><span style="color:#3f8058">:</span> match_cond1_ct <span style="color:#3f8058">=</span> dcpu_dat_dc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load data</span> 1149 <span style="color:#f67400">3'b101</span><span style="color:#3f8058">:</span> match_cond1_ct <span style="color:#3f8058">=</span> dcpu_dat_lsu<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// store data</span> 1150 <span style="color:#f67400">3'b110</span><span style="color:#3f8058">:</span> match_cond1_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load/store EA</span> 1151 <span style="font-weight:bold">default</span><span style="color:#3f8058">:</span>match_cond1_ct <span style="color:#3f8058">=</span> dcpu_we_i <span style="color:#3f8058">?</span> dcpu_dat_lsu <span style="color:#3f8058">:</span> dcpu_dat_dc<span style="color:#3f8058">;</span> 1152 <span style="font-weight:bold">endcase</span> 1153 1154 <span style="color:#7a7c7d">//</span> 1155 <span style="color:#7a7c7d">// When To Compare (Match Condition 1)</span> 1156 <span style="color:#7a7c7d">//</span> 1157 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dcr1 <span style="color:#2980b9">or</span> dcpu_cycstb_i<span style="color:#3f8058">)</span> 1158 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CT</span><span style="color:#3f8058">])</span> <span style="color:#7a7c7d">// synopsys parallel_case</span> 1159 <span style="color:#f67400">3'b000</span><span style="color:#3f8058">:</span> match_cond1_stb <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> <span style="color:#7a7c7d">//comparison disabled</span> 1160 <span style="color:#f67400">3'b001</span><span style="color:#3f8058">:</span> match_cond1_stb <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// insn fetch EA</span> 1161 <span style="font-weight:bold">default</span><span style="color:#3f8058">:</span>match_cond1_stb <span style="color:#3f8058">=</span> dcpu_cycstb_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// any load/store</span> 1162 <span style="font-weight:bold">endcase</span> 1163 1164 <span style="color:#7a7c7d">//</span> 1165 <span style="color:#7a7c7d">// Match Condition 1</span> 1166 <span style="color:#7a7c7d">//</span> 1167 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>match_cond1_stb <span style="color:#2980b9">or</span> dcr1 <span style="color:#2980b9">or</span> dvr1 <span style="color:#2980b9">or</span> match_cond1_ct<span style="color:#3f8058">)</span> 1168 <span style="font-weight:bold">casex</span> <span style="color:#3f8058">({</span>match_cond1_stb<span style="color:#3f8058">,</span> dcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CC</span><span style="color:#3f8058">]})</span> 1169 <span style="color:#f67400">4'b0_xxx</span><span style="color:#3f8058">,</span> 1170 <span style="color:#f67400">4'b1_000</span><span style="color:#3f8058">,</span> 1171 <span style="color:#f67400">4'b1_111</span><span style="color:#3f8058">:</span> match1 <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1172 <span style="color:#f67400">4'b1_001</span><span style="color:#3f8058">:</span> match1 <span style="color:#3f8058">=</span> 1173 <span style="color:#3f8058">({(</span>match_cond1_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond1_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">==</span> 1174 <span style="color:#3f8058">{(</span>dvr1<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr1<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1175 <span style="color:#f67400">4'b1_010</span><span style="color:#3f8058">:</span> match1 <span style="color:#3f8058">=</span> 1176 <span style="color:#3f8058">({(</span>match_cond1_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond1_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058"><</span> 1177 <span style="color:#3f8058">{(</span>dvr1<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr1<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1178 <span style="color:#f67400">4'b1_011</span><span style="color:#3f8058">:</span> match1 <span style="color:#3f8058">=</span> 1179 <span style="color:#3f8058">({(</span>match_cond1_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond1_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058"><=</span> 1180 <span style="color:#3f8058">{(</span>dvr1<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr1<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1181 <span style="color:#f67400">4'b1_100</span><span style="color:#3f8058">:</span> match1 <span style="color:#3f8058">=</span> 1182 <span style="color:#3f8058">({(</span>match_cond1_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond1_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">></span> 1183 <span style="color:#3f8058">{(</span>dvr1<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr1<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1184 <span style="color:#f67400">4'b1_101</span><span style="color:#3f8058">:</span> match1 <span style="color:#3f8058">=</span> 1185 <span style="color:#3f8058">({(</span>match_cond1_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond1_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">>=</span> 1186 <span style="color:#3f8058">{(</span>dvr1<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr1<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1187 <span style="color:#f67400">4'b1_110</span><span style="color:#3f8058">:</span> match1 <span style="color:#3f8058">=</span> 1188 <span style="color:#3f8058">({(</span>match_cond1_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond1_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">!=</span> 1189 <span style="color:#3f8058">{(</span>dvr1<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr1<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1190 <span style="font-weight:bold">endcase</span> 1191 1192 <span style="color:#7a7c7d">//</span> 1193 <span style="color:#7a7c7d">// Watchpoint 1</span> 1194 <span style="color:#7a7c7d">//</span> 1195 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dmr1 <span style="color:#2980b9">or</span> match1 <span style="color:#2980b9">or</span> wp<span style="color:#3f8058">)</span> 1196 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dmr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DMR1_CW1</span><span style="color:#3f8058">])</span> 1197 <span style="color:#f67400">2'b00</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">1</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match1<span style="color:#3f8058">;</span> 1198 <span style="color:#f67400">2'b01</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">1</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match1 <span style="color:#3f8058">&</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 1199 <span style="color:#f67400">2'b10</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">1</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match1 <span style="color:#3f8058">|</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">0</span><span style="color:#3f8058">];</span> 1200 <span style="color:#f67400">2'b11</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">1</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1201 <span style="font-weight:bold">endcase</span> 1202 1203 <span style="color:#7a7c7d">//</span> 1204 <span style="color:#7a7c7d">// Compare To What (Match Condition 2)</span> 1205 <span style="color:#7a7c7d">//</span> 1206 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dcr2 <span style="color:#2980b9">or</span> id_pc <span style="color:#2980b9">or</span> dcpu_adr_i <span style="color:#2980b9">or</span> dcpu_dat_dc 1207 <span style="color:#2980b9">or</span> dcpu_dat_lsu <span style="color:#2980b9">or</span> dcpu_we_i<span style="color:#3f8058">)</span> 1208 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dcr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CT</span><span style="color:#3f8058">])</span> <span style="color:#7a7c7d">// synopsys parallel_case</span> 1209 <span style="color:#f67400">3'b001</span><span style="color:#3f8058">:</span> match_cond2_ct <span style="color:#3f8058">=</span> id_pc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// insn fetch EA</span> 1210 <span style="color:#f67400">3'b010</span><span style="color:#3f8058">:</span> match_cond2_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load EA</span> 1211 <span style="color:#f67400">3'b011</span><span style="color:#3f8058">:</span> match_cond2_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// store EA</span> 1212 <span style="color:#f67400">3'b100</span><span style="color:#3f8058">:</span> match_cond2_ct <span style="color:#3f8058">=</span> dcpu_dat_dc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load data</span> 1213 <span style="color:#f67400">3'b101</span><span style="color:#3f8058">:</span> match_cond2_ct <span style="color:#3f8058">=</span> dcpu_dat_lsu<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// store data</span> 1214 <span style="color:#f67400">3'b110</span><span style="color:#3f8058">:</span> match_cond2_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load/store EA</span> 1215 <span style="font-weight:bold">default</span><span style="color:#3f8058">:</span>match_cond2_ct <span style="color:#3f8058">=</span> dcpu_we_i <span style="color:#3f8058">?</span> dcpu_dat_lsu <span style="color:#3f8058">:</span> dcpu_dat_dc<span style="color:#3f8058">;</span> 1216 <span style="font-weight:bold">endcase</span> 1217 1218 <span style="color:#7a7c7d">//</span> 1219 <span style="color:#7a7c7d">// When To Compare (Match Condition 2)</span> 1220 <span style="color:#7a7c7d">//</span> 1221 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dcr2 <span style="color:#2980b9">or</span> dcpu_cycstb_i<span style="color:#3f8058">)</span> 1222 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dcr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CT</span><span style="color:#3f8058">])</span> <span style="color:#7a7c7d">// synopsys parallel_case</span> 1223 <span style="color:#f67400">3'b000</span><span style="color:#3f8058">:</span> match_cond2_stb <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> <span style="color:#7a7c7d">//comparison disabled</span> 1224 <span style="color:#f67400">3'b001</span><span style="color:#3f8058">:</span> match_cond2_stb <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// insn fetch EA</span> 1225 <span style="font-weight:bold">default</span><span style="color:#3f8058">:</span>match_cond2_stb <span style="color:#3f8058">=</span> dcpu_cycstb_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// any load/store</span> 1226 <span style="font-weight:bold">endcase</span> 1227 1228 <span style="color:#7a7c7d">//</span> 1229 <span style="color:#7a7c7d">// Match Condition 2</span> 1230 <span style="color:#7a7c7d">//</span> 1231 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>match_cond2_stb <span style="color:#2980b9">or</span> dcr2 <span style="color:#2980b9">or</span> dvr2 <span style="color:#2980b9">or</span> match_cond2_ct<span style="color:#3f8058">)</span> 1232 <span style="font-weight:bold">casex</span> <span style="color:#3f8058">({</span>match_cond2_stb<span style="color:#3f8058">,</span> dcr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CC</span><span style="color:#3f8058">]})</span> 1233 <span style="color:#f67400">4'b0_xxx</span><span style="color:#3f8058">,</span> 1234 <span style="color:#f67400">4'b1_000</span><span style="color:#3f8058">,</span> 1235 <span style="color:#f67400">4'b1_111</span><span style="color:#3f8058">:</span> match2 <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1236 <span style="color:#f67400">4'b1_001</span><span style="color:#3f8058">:</span> match2 <span style="color:#3f8058">=</span> 1237 <span style="color:#3f8058">({(</span>match_cond2_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond2_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">==</span> 1238 <span style="color:#3f8058">{(</span>dvr2<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr2<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1239 <span style="color:#f67400">4'b1_010</span><span style="color:#3f8058">:</span> match2 <span style="color:#3f8058">=</span> 1240 <span style="color:#3f8058">({(</span>match_cond2_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond2_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058"><</span> 1241 <span style="color:#3f8058">{(</span>dvr2<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr2<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1242 <span style="color:#f67400">4'b1_011</span><span style="color:#3f8058">:</span> match2 <span style="color:#3f8058">=</span> 1243 <span style="color:#3f8058">({(</span>match_cond2_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond2_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058"><=</span> 1244 <span style="color:#3f8058">{(</span>dvr2<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr2<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1245 <span style="color:#f67400">4'b1_100</span><span style="color:#3f8058">:</span> match2 <span style="color:#3f8058">=</span> 1246 <span style="color:#3f8058">({(</span>match_cond2_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond2_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">></span> 1247 <span style="color:#3f8058">{(</span>dvr2<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr2<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1248 <span style="color:#f67400">4'b1_101</span><span style="color:#3f8058">:</span> match2 <span style="color:#3f8058">=</span> 1249 <span style="color:#3f8058">({(</span>match_cond2_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond2_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">>=</span> 1250 <span style="color:#3f8058">{(</span>dvr2<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr2<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1251 <span style="color:#f67400">4'b1_110</span><span style="color:#3f8058">:</span> match2 <span style="color:#3f8058">=</span> 1252 <span style="color:#3f8058">({(</span>match_cond2_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond2_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">!=</span> 1253 <span style="color:#3f8058">{(</span>dvr2<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr2<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1254 <span style="font-weight:bold">endcase</span> 1255 1256 <span style="color:#7a7c7d">//</span> 1257 <span style="color:#7a7c7d">// Watchpoint 2</span> 1258 <span style="color:#7a7c7d">//</span> 1259 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dmr1 <span style="color:#2980b9">or</span> match2 <span style="color:#2980b9">or</span> wp<span style="color:#3f8058">)</span> 1260 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dmr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DMR1_CW2</span><span style="color:#3f8058">])</span> 1261 <span style="color:#f67400">2'b00</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">2</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match2<span style="color:#3f8058">;</span> 1262 <span style="color:#f67400">2'b01</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">2</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match2 <span style="color:#3f8058">&</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">1</span><span style="color:#3f8058">];</span> 1263 <span style="color:#f67400">2'b10</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">2</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match2 <span style="color:#3f8058">|</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">1</span><span style="color:#3f8058">];</span> 1264 <span style="color:#f67400">2'b11</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">2</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1265 <span style="font-weight:bold">endcase</span> 1266 1267 <span style="color:#7a7c7d">//</span> 1268 <span style="color:#7a7c7d">// Compare To What (Match Condition 3)</span> 1269 <span style="color:#7a7c7d">//</span> 1270 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dcr3 <span style="color:#2980b9">or</span> id_pc <span style="color:#2980b9">or</span> dcpu_adr_i <span style="color:#2980b9">or</span> dcpu_dat_dc 1271 <span style="color:#2980b9">or</span> dcpu_dat_lsu <span style="color:#2980b9">or</span> dcpu_we_i<span style="color:#3f8058">)</span> 1272 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dcr3<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CT</span><span style="color:#3f8058">])</span> <span style="color:#7a7c7d">// synopsys parallel_case</span> 1273 <span style="color:#f67400">3'b001</span><span style="color:#3f8058">:</span> match_cond3_ct <span style="color:#3f8058">=</span> id_pc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// insn fetch EA</span> 1274 <span style="color:#f67400">3'b010</span><span style="color:#3f8058">:</span> match_cond3_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load EA</span> 1275 <span style="color:#f67400">3'b011</span><span style="color:#3f8058">:</span> match_cond3_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// store EA</span> 1276 <span style="color:#f67400">3'b100</span><span style="color:#3f8058">:</span> match_cond3_ct <span style="color:#3f8058">=</span> dcpu_dat_dc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load data</span> 1277 <span style="color:#f67400">3'b101</span><span style="color:#3f8058">:</span> match_cond3_ct <span style="color:#3f8058">=</span> dcpu_dat_lsu<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// store data</span> 1278 <span style="color:#f67400">3'b110</span><span style="color:#3f8058">:</span> match_cond3_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load/store EA</span> 1279 <span style="font-weight:bold">default</span><span style="color:#3f8058">:</span>match_cond3_ct <span style="color:#3f8058">=</span> dcpu_we_i <span style="color:#3f8058">?</span> dcpu_dat_lsu <span style="color:#3f8058">:</span> dcpu_dat_dc<span style="color:#3f8058">;</span> 1280 <span style="font-weight:bold">endcase</span> 1281 1282 <span style="color:#7a7c7d">//</span> 1283 <span style="color:#7a7c7d">// When To Compare (Match Condition 3)</span> 1284 <span style="color:#7a7c7d">//</span> 1285 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dcr3 <span style="color:#2980b9">or</span> dcpu_cycstb_i<span style="color:#3f8058">)</span> 1286 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dcr3<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CT</span><span style="color:#3f8058">])</span> <span style="color:#7a7c7d">// synopsys parallel_case</span> 1287 <span style="color:#f67400">3'b000</span><span style="color:#3f8058">:</span> match_cond3_stb <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> <span style="color:#7a7c7d">//comparison disabled</span> 1288 <span style="color:#f67400">3'b001</span><span style="color:#3f8058">:</span> match_cond3_stb <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// insn fetch EA</span> 1289 <span style="font-weight:bold">default</span><span style="color:#3f8058">:</span>match_cond3_stb <span style="color:#3f8058">=</span> dcpu_cycstb_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// any load/store</span> 1290 <span style="font-weight:bold">endcase</span> 1291 1292 <span style="color:#7a7c7d">//</span> 1293 <span style="color:#7a7c7d">// Match Condition 3</span> 1294 <span style="color:#7a7c7d">//</span> 1295 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>match_cond3_stb <span style="color:#2980b9">or</span> dcr3 <span style="color:#2980b9">or</span> dvr3 <span style="color:#2980b9">or</span> match_cond3_ct<span style="color:#3f8058">)</span> 1296 <span style="font-weight:bold">casex</span> <span style="color:#3f8058">({</span>match_cond3_stb<span style="color:#3f8058">,</span> dcr3<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CC</span><span style="color:#3f8058">]})</span> 1297 <span style="color:#f67400">4'b0_xxx</span><span style="color:#3f8058">,</span> 1298 <span style="color:#f67400">4'b1_000</span><span style="color:#3f8058">,</span> 1299 <span style="color:#f67400">4'b1_111</span><span style="color:#3f8058">:</span> match3 <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1300 <span style="color:#f67400">4'b1_001</span><span style="color:#3f8058">:</span> match3 <span style="color:#3f8058">=</span> 1301 <span style="color:#3f8058">({(</span>match_cond3_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr3<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond3_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">==</span> 1302 <span style="color:#3f8058">{(</span>dvr3<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr3<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr3<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1303 <span style="color:#f67400">4'b1_010</span><span style="color:#3f8058">:</span> match3 <span style="color:#3f8058">=</span> 1304 <span style="color:#3f8058">({(</span>match_cond3_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr3<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond3_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058"><</span> 1305 <span style="color:#3f8058">{(</span>dvr3<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr3<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr3<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1306 <span style="color:#f67400">4'b1_011</span><span style="color:#3f8058">:</span> match3 <span style="color:#3f8058">=</span> 1307 <span style="color:#3f8058">({(</span>match_cond3_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr3<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond3_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058"><=</span> 1308 <span style="color:#3f8058">{(</span>dvr3<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr3<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr3<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1309 <span style="color:#f67400">4'b1_100</span><span style="color:#3f8058">:</span> match3 <span style="color:#3f8058">=</span> 1310 <span style="color:#3f8058">({(</span>match_cond3_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr3<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond3_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">></span> 1311 <span style="color:#3f8058">{(</span>dvr3<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr3<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr3<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1312 <span style="color:#f67400">4'b1_101</span><span style="color:#3f8058">:</span> match3 <span style="color:#3f8058">=</span> 1313 <span style="color:#3f8058">({(</span>match_cond3_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr3<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond3_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">>=</span> 1314 <span style="color:#3f8058">{(</span>dvr3<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr3<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr3<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1315 <span style="color:#f67400">4'b1_110</span><span style="color:#3f8058">:</span> match3 <span style="color:#3f8058">=</span> 1316 <span style="color:#3f8058">({(</span>match_cond3_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr3<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond3_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">!=</span> 1317 <span style="color:#3f8058">{(</span>dvr3<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr3<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr3<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1318 <span style="font-weight:bold">endcase</span> 1319 1320 <span style="color:#7a7c7d">//</span> 1321 <span style="color:#7a7c7d">// Watchpoint 3</span> 1322 <span style="color:#7a7c7d">//</span> 1323 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dmr1 <span style="color:#2980b9">or</span> match3 <span style="color:#2980b9">or</span> wp<span style="color:#3f8058">)</span> 1324 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dmr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DMR1_CW3</span><span style="color:#3f8058">])</span> 1325 <span style="color:#f67400">2'b00</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">3</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match3<span style="color:#3f8058">;</span> 1326 <span style="color:#f67400">2'b01</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">3</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match3 <span style="color:#3f8058">&</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">2</span><span style="color:#3f8058">];</span> 1327 <span style="color:#f67400">2'b10</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">3</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match3 <span style="color:#3f8058">|</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">2</span><span style="color:#3f8058">];</span> 1328 <span style="color:#f67400">2'b11</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">3</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1329 <span style="font-weight:bold">endcase</span> 1330 1331 <span style="color:#7a7c7d">//</span> 1332 <span style="color:#7a7c7d">// Compare To What (Match Condition 4)</span> 1333 <span style="color:#7a7c7d">//</span> 1334 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dcr4 <span style="color:#2980b9">or</span> id_pc <span style="color:#2980b9">or</span> dcpu_adr_i <span style="color:#2980b9">or</span> dcpu_dat_dc 1335 <span style="color:#2980b9">or</span> dcpu_dat_lsu <span style="color:#2980b9">or</span> dcpu_we_i<span style="color:#3f8058">)</span> 1336 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dcr4<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CT</span><span style="color:#3f8058">])</span> <span style="color:#7a7c7d">// synopsys parallel_case</span> 1337 <span style="color:#f67400">3'b001</span><span style="color:#3f8058">:</span> match_cond4_ct <span style="color:#3f8058">=</span> id_pc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// insn fetch EA</span> 1338 <span style="color:#f67400">3'b010</span><span style="color:#3f8058">:</span> match_cond4_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load EA</span> 1339 <span style="color:#f67400">3'b011</span><span style="color:#3f8058">:</span> match_cond4_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// store EA</span> 1340 <span style="color:#f67400">3'b100</span><span style="color:#3f8058">:</span> match_cond4_ct <span style="color:#3f8058">=</span> dcpu_dat_dc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load data</span> 1341 <span style="color:#f67400">3'b101</span><span style="color:#3f8058">:</span> match_cond4_ct <span style="color:#3f8058">=</span> dcpu_dat_lsu<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// store data</span> 1342 <span style="color:#f67400">3'b110</span><span style="color:#3f8058">:</span> match_cond4_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load/store EA</span> 1343 <span style="font-weight:bold">default</span><span style="color:#3f8058">:</span>match_cond4_ct <span style="color:#3f8058">=</span> dcpu_we_i <span style="color:#3f8058">?</span> dcpu_dat_lsu <span style="color:#3f8058">:</span> dcpu_dat_dc<span style="color:#3f8058">;</span> 1344 <span style="font-weight:bold">endcase</span> 1345 1346 <span style="color:#7a7c7d">//</span> 1347 <span style="color:#7a7c7d">// When To Compare (Match Condition 4)</span> 1348 <span style="color:#7a7c7d">//</span> 1349 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dcr4 <span style="color:#2980b9">or</span> dcpu_cycstb_i<span style="color:#3f8058">)</span> 1350 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dcr4<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CT</span><span style="color:#3f8058">])</span> <span style="color:#7a7c7d">// synopsys parallel_case</span> 1351 <span style="color:#f67400">3'b000</span><span style="color:#3f8058">:</span> match_cond4_stb <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> <span style="color:#7a7c7d">//comparison disabled</span> 1352 <span style="color:#f67400">3'b001</span><span style="color:#3f8058">:</span> match_cond4_stb <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// insn fetch EA</span> 1353 <span style="font-weight:bold">default</span><span style="color:#3f8058">:</span>match_cond4_stb <span style="color:#3f8058">=</span> dcpu_cycstb_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// any load/store</span> 1354 <span style="font-weight:bold">endcase</span> 1355 1356 <span style="color:#7a7c7d">//</span> 1357 <span style="color:#7a7c7d">// Match Condition 4</span> 1358 <span style="color:#7a7c7d">//</span> 1359 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>match_cond4_stb <span style="color:#2980b9">or</span> dcr4 <span style="color:#2980b9">or</span> dvr4 <span style="color:#2980b9">or</span> match_cond4_ct<span style="color:#3f8058">)</span> 1360 <span style="font-weight:bold">casex</span> <span style="color:#3f8058">({</span>match_cond4_stb<span style="color:#3f8058">,</span> dcr4<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CC</span><span style="color:#3f8058">]})</span> 1361 <span style="color:#f67400">4'b0_xxx</span><span style="color:#3f8058">,</span> 1362 <span style="color:#f67400">4'b1_000</span><span style="color:#3f8058">,</span> 1363 <span style="color:#f67400">4'b1_111</span><span style="color:#3f8058">:</span> match4 <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1364 <span style="color:#f67400">4'b1_001</span><span style="color:#3f8058">:</span> match4 <span style="color:#3f8058">=</span> 1365 <span style="color:#3f8058">({(</span>match_cond4_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr4<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond4_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">==</span> 1366 <span style="color:#3f8058">{(</span>dvr4<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr4<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr4<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1367 <span style="color:#f67400">4'b1_010</span><span style="color:#3f8058">:</span> match4 <span style="color:#3f8058">=</span> 1368 <span style="color:#3f8058">({(</span>match_cond4_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr4<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond4_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058"><</span> 1369 <span style="color:#3f8058">{(</span>dvr4<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr4<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr4<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1370 <span style="color:#f67400">4'b1_011</span><span style="color:#3f8058">:</span> match4 <span style="color:#3f8058">=</span> 1371 <span style="color:#3f8058">({(</span>match_cond4_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr4<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond4_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058"><=</span> 1372 <span style="color:#3f8058">{(</span>dvr4<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr4<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr4<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1373 <span style="color:#f67400">4'b1_100</span><span style="color:#3f8058">:</span> match4 <span style="color:#3f8058">=</span> 1374 <span style="color:#3f8058">({(</span>match_cond4_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr4<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond4_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">></span> 1375 <span style="color:#3f8058">{(</span>dvr4<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr4<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr4<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1376 <span style="color:#f67400">4'b1_101</span><span style="color:#3f8058">:</span> match4 <span style="color:#3f8058">=</span> 1377 <span style="color:#3f8058">({(</span>match_cond4_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr4<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond4_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">>=</span> 1378 <span style="color:#3f8058">{(</span>dvr4<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr4<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr4<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1379 <span style="color:#f67400">4'b1_110</span><span style="color:#3f8058">:</span> match4 <span style="color:#3f8058">=</span> 1380 <span style="color:#3f8058">({(</span>match_cond4_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr4<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond4_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">!=</span> 1381 <span style="color:#3f8058">{(</span>dvr4<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr4<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr4<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1382 <span style="font-weight:bold">endcase</span> 1383 1384 <span style="color:#7a7c7d">//</span> 1385 <span style="color:#7a7c7d">// Watchpoint 4</span> 1386 <span style="color:#7a7c7d">//</span> 1387 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dmr1 <span style="color:#2980b9">or</span> match4 <span style="color:#2980b9">or</span> wp<span style="color:#3f8058">)</span> 1388 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dmr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DMR1_CW4</span><span style="color:#3f8058">])</span> 1389 <span style="color:#f67400">2'b00</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">4</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match4<span style="color:#3f8058">;</span> 1390 <span style="color:#f67400">2'b01</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">4</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match4 <span style="color:#3f8058">&</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">3</span><span style="color:#3f8058">];</span> 1391 <span style="color:#f67400">2'b10</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">4</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match4 <span style="color:#3f8058">|</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">3</span><span style="color:#3f8058">];</span> 1392 <span style="color:#f67400">2'b11</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">4</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1393 <span style="font-weight:bold">endcase</span> 1394 1395 <span style="color:#7a7c7d">//</span> 1396 <span style="color:#7a7c7d">// Compare To What (Match Condition 5)</span> 1397 <span style="color:#7a7c7d">//</span> 1398 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dcr5 <span style="color:#2980b9">or</span> id_pc <span style="color:#2980b9">or</span> dcpu_adr_i <span style="color:#2980b9">or</span> dcpu_dat_dc 1399 <span style="color:#2980b9">or</span> dcpu_dat_lsu <span style="color:#2980b9">or</span> dcpu_we_i<span style="color:#3f8058">)</span> 1400 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dcr5<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CT</span><span style="color:#3f8058">])</span> <span style="color:#7a7c7d">// synopsys parallel_case</span> 1401 <span style="color:#f67400">3'b001</span><span style="color:#3f8058">:</span> match_cond5_ct <span style="color:#3f8058">=</span> id_pc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// insn fetch EA</span> 1402 <span style="color:#f67400">3'b010</span><span style="color:#3f8058">:</span> match_cond5_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load EA</span> 1403 <span style="color:#f67400">3'b011</span><span style="color:#3f8058">:</span> match_cond5_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// store EA</span> 1404 <span style="color:#f67400">3'b100</span><span style="color:#3f8058">:</span> match_cond5_ct <span style="color:#3f8058">=</span> dcpu_dat_dc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load data</span> 1405 <span style="color:#f67400">3'b101</span><span style="color:#3f8058">:</span> match_cond5_ct <span style="color:#3f8058">=</span> dcpu_dat_lsu<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// store data</span> 1406 <span style="color:#f67400">3'b110</span><span style="color:#3f8058">:</span> match_cond5_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load/store EA</span> 1407 <span style="font-weight:bold">default</span><span style="color:#3f8058">:</span>match_cond5_ct <span style="color:#3f8058">=</span> dcpu_we_i <span style="color:#3f8058">?</span> dcpu_dat_lsu <span style="color:#3f8058">:</span> dcpu_dat_dc<span style="color:#3f8058">;</span> 1408 <span style="font-weight:bold">endcase</span> 1409 1410 <span style="color:#7a7c7d">//</span> 1411 <span style="color:#7a7c7d">// When To Compare (Match Condition 5)</span> 1412 <span style="color:#7a7c7d">//</span> 1413 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dcr5 <span style="color:#2980b9">or</span> dcpu_cycstb_i<span style="color:#3f8058">)</span> 1414 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dcr5<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CT</span><span style="color:#3f8058">])</span> <span style="color:#7a7c7d">// synopsys parallel_case</span> 1415 <span style="color:#f67400">3'b000</span><span style="color:#3f8058">:</span> match_cond5_stb <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> <span style="color:#7a7c7d">//comparison disabled</span> 1416 <span style="color:#f67400">3'b001</span><span style="color:#3f8058">:</span> match_cond5_stb <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// insn fetch EA</span> 1417 <span style="font-weight:bold">default</span><span style="color:#3f8058">:</span>match_cond5_stb <span style="color:#3f8058">=</span> dcpu_cycstb_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// any load/store</span> 1418 <span style="font-weight:bold">endcase</span> 1419 1420 <span style="color:#7a7c7d">//</span> 1421 <span style="color:#7a7c7d">// Match Condition 5</span> 1422 <span style="color:#7a7c7d">//</span> 1423 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>match_cond5_stb <span style="color:#2980b9">or</span> dcr5 <span style="color:#2980b9">or</span> dvr5 <span style="color:#2980b9">or</span> match_cond5_ct<span style="color:#3f8058">)</span> 1424 <span style="font-weight:bold">casex</span> <span style="color:#3f8058">({</span>match_cond5_stb<span style="color:#3f8058">,</span> dcr5<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CC</span><span style="color:#3f8058">]})</span> 1425 <span style="color:#f67400">4'b0_xxx</span><span style="color:#3f8058">,</span> 1426 <span style="color:#f67400">4'b1_000</span><span style="color:#3f8058">,</span> 1427 <span style="color:#f67400">4'b1_111</span><span style="color:#3f8058">:</span> match5 <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1428 <span style="color:#f67400">4'b1_001</span><span style="color:#3f8058">:</span> match5 <span style="color:#3f8058">=</span> 1429 <span style="color:#3f8058">({(</span>match_cond5_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr5<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond5_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">==</span> 1430 <span style="color:#3f8058">{(</span>dvr5<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr5<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr5<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1431 <span style="color:#f67400">4'b1_010</span><span style="color:#3f8058">:</span> match5 <span style="color:#3f8058">=</span> 1432 <span style="color:#3f8058">({(</span>match_cond5_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr5<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond5_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058"><</span> 1433 <span style="color:#3f8058">{(</span>dvr5<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr5<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr5<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1434 <span style="color:#f67400">4'b1_011</span><span style="color:#3f8058">:</span> match5 <span style="color:#3f8058">=</span> 1435 <span style="color:#3f8058">({(</span>match_cond5_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr5<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond5_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058"><=</span> 1436 <span style="color:#3f8058">{(</span>dvr5<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr5<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr5<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1437 <span style="color:#f67400">4'b1_100</span><span style="color:#3f8058">:</span> match5 <span style="color:#3f8058">=</span> 1438 <span style="color:#3f8058">({(</span>match_cond5_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr5<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond5_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">></span> 1439 <span style="color:#3f8058">{(</span>dvr5<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr5<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr5<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1440 <span style="color:#f67400">4'b1_101</span><span style="color:#3f8058">:</span> match5 <span style="color:#3f8058">=</span> 1441 <span style="color:#3f8058">({(</span>match_cond5_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr5<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond5_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">>=</span> 1442 <span style="color:#3f8058">{(</span>dvr5<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr5<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr5<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1443 <span style="color:#f67400">4'b1_110</span><span style="color:#3f8058">:</span> match5 <span style="color:#3f8058">=</span> 1444 <span style="color:#3f8058">({(</span>match_cond5_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr5<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond5_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">!=</span> 1445 <span style="color:#3f8058">{(</span>dvr5<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr5<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr5<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1446 <span style="font-weight:bold">endcase</span> 1447 1448 <span style="color:#7a7c7d">//</span> 1449 <span style="color:#7a7c7d">// Watchpoint 5</span> 1450 <span style="color:#7a7c7d">//</span> 1451 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dmr1 <span style="color:#2980b9">or</span> match5 <span style="color:#2980b9">or</span> wp<span style="color:#3f8058">)</span> 1452 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dmr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DMR1_CW5</span><span style="color:#3f8058">])</span> 1453 <span style="color:#f67400">2'b00</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">5</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match5<span style="color:#3f8058">;</span> 1454 <span style="color:#f67400">2'b01</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">5</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match5 <span style="color:#3f8058">&</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">4</span><span style="color:#3f8058">];</span> 1455 <span style="color:#f67400">2'b10</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">5</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match5 <span style="color:#3f8058">|</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">4</span><span style="color:#3f8058">];</span> 1456 <span style="color:#f67400">2'b11</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">5</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1457 <span style="font-weight:bold">endcase</span> 1458 1459 <span style="color:#7a7c7d">//</span> 1460 <span style="color:#7a7c7d">// Compare To What (Match Condition 6)</span> 1461 <span style="color:#7a7c7d">//</span> 1462 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dcr6 <span style="color:#2980b9">or</span> id_pc <span style="color:#2980b9">or</span> dcpu_adr_i <span style="color:#2980b9">or</span> dcpu_dat_dc 1463 <span style="color:#2980b9">or</span> dcpu_dat_lsu <span style="color:#2980b9">or</span> dcpu_we_i<span style="color:#3f8058">)</span> 1464 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dcr6<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CT</span><span style="color:#3f8058">])</span> <span style="color:#7a7c7d">// synopsys parallel_case</span> 1465 <span style="color:#f67400">3'b001</span><span style="color:#3f8058">:</span> match_cond6_ct <span style="color:#3f8058">=</span> id_pc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// insn fetch EA</span> 1466 <span style="color:#f67400">3'b010</span><span style="color:#3f8058">:</span> match_cond6_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load EA</span> 1467 <span style="color:#f67400">3'b011</span><span style="color:#3f8058">:</span> match_cond6_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// store EA</span> 1468 <span style="color:#f67400">3'b100</span><span style="color:#3f8058">:</span> match_cond6_ct <span style="color:#3f8058">=</span> dcpu_dat_dc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load data</span> 1469 <span style="color:#f67400">3'b101</span><span style="color:#3f8058">:</span> match_cond6_ct <span style="color:#3f8058">=</span> dcpu_dat_lsu<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// store data</span> 1470 <span style="color:#f67400">3'b110</span><span style="color:#3f8058">:</span> match_cond6_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load/store EA</span> 1471 <span style="font-weight:bold">default</span><span style="color:#3f8058">:</span>match_cond6_ct <span style="color:#3f8058">=</span> dcpu_we_i <span style="color:#3f8058">?</span> dcpu_dat_lsu <span style="color:#3f8058">:</span> dcpu_dat_dc<span style="color:#3f8058">;</span> 1472 <span style="font-weight:bold">endcase</span> 1473 1474 <span style="color:#7a7c7d">//</span> 1475 <span style="color:#7a7c7d">// When To Compare (Match Condition 6)</span> 1476 <span style="color:#7a7c7d">//</span> 1477 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dcr6 <span style="color:#2980b9">or</span> dcpu_cycstb_i<span style="color:#3f8058">)</span> 1478 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dcr6<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CT</span><span style="color:#3f8058">])</span> <span style="color:#7a7c7d">// synopsys parallel_case</span> 1479 <span style="color:#f67400">3'b000</span><span style="color:#3f8058">:</span> match_cond6_stb <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> <span style="color:#7a7c7d">//comparison disabled</span> 1480 <span style="color:#f67400">3'b001</span><span style="color:#3f8058">:</span> match_cond6_stb <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// insn fetch EA</span> 1481 <span style="font-weight:bold">default</span><span style="color:#3f8058">:</span>match_cond6_stb <span style="color:#3f8058">=</span> dcpu_cycstb_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// any load/store</span> 1482 <span style="font-weight:bold">endcase</span> 1483 1484 <span style="color:#7a7c7d">//</span> 1485 <span style="color:#7a7c7d">// Match Condition 6</span> 1486 <span style="color:#7a7c7d">//</span> 1487 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>match_cond6_stb <span style="color:#2980b9">or</span> dcr6 <span style="color:#2980b9">or</span> dvr6 <span style="color:#2980b9">or</span> match_cond6_ct<span style="color:#3f8058">)</span> 1488 <span style="font-weight:bold">casex</span> <span style="color:#3f8058">({</span>match_cond6_stb<span style="color:#3f8058">,</span> dcr6<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CC</span><span style="color:#3f8058">]})</span> 1489 <span style="color:#f67400">4'b0_xxx</span><span style="color:#3f8058">,</span> 1490 <span style="color:#f67400">4'b1_000</span><span style="color:#3f8058">,</span> 1491 <span style="color:#f67400">4'b1_111</span><span style="color:#3f8058">:</span> match6 <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1492 <span style="color:#f67400">4'b1_001</span><span style="color:#3f8058">:</span> match6 <span style="color:#3f8058">=</span> 1493 <span style="color:#3f8058">({(</span>match_cond6_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr6<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond6_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">==</span> 1494 <span style="color:#3f8058">{(</span>dvr6<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr6<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr6<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1495 <span style="color:#f67400">4'b1_010</span><span style="color:#3f8058">:</span> match6 <span style="color:#3f8058">=</span> 1496 <span style="color:#3f8058">({(</span>match_cond6_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr6<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond6_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058"><</span> 1497 <span style="color:#3f8058">{(</span>dvr6<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr6<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr6<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1498 <span style="color:#f67400">4'b1_011</span><span style="color:#3f8058">:</span> match6 <span style="color:#3f8058">=</span> 1499 <span style="color:#3f8058">({(</span>match_cond6_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr6<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond6_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058"><=</span> 1500 <span style="color:#3f8058">{(</span>dvr6<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr6<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr6<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1501 <span style="color:#f67400">4'b1_100</span><span style="color:#3f8058">:</span> match6 <span style="color:#3f8058">=</span> 1502 <span style="color:#3f8058">({(</span>match_cond6_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr6<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond6_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">></span> 1503 <span style="color:#3f8058">{(</span>dvr6<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr6<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr6<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1504 <span style="color:#f67400">4'b1_101</span><span style="color:#3f8058">:</span> match6 <span style="color:#3f8058">=</span> 1505 <span style="color:#3f8058">({(</span>match_cond6_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr6<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond6_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">>=</span> 1506 <span style="color:#3f8058">{(</span>dvr6<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr6<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr6<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1507 <span style="color:#f67400">4'b1_110</span><span style="color:#3f8058">:</span> match6 <span style="color:#3f8058">=</span> 1508 <span style="color:#3f8058">({(</span>match_cond6_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr6<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond6_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">!=</span> 1509 <span style="color:#3f8058">{(</span>dvr6<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr6<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr6<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1510 <span style="font-weight:bold">endcase</span> 1511 1512 <span style="color:#7a7c7d">//</span> 1513 <span style="color:#7a7c7d">// Watchpoint 6</span> 1514 <span style="color:#7a7c7d">//</span> 1515 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dmr1 <span style="color:#2980b9">or</span> match6 <span style="color:#2980b9">or</span> wp<span style="color:#3f8058">)</span> 1516 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dmr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DMR1_CW6</span><span style="color:#3f8058">])</span> 1517 <span style="color:#f67400">2'b00</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">6</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match6<span style="color:#3f8058">;</span> 1518 <span style="color:#f67400">2'b01</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">6</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match6 <span style="color:#3f8058">&</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">5</span><span style="color:#3f8058">];</span> 1519 <span style="color:#f67400">2'b10</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">6</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match6 <span style="color:#3f8058">|</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">5</span><span style="color:#3f8058">];</span> 1520 <span style="color:#f67400">2'b11</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">6</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1521 <span style="font-weight:bold">endcase</span> 1522 1523 <span style="color:#7a7c7d">//</span> 1524 <span style="color:#7a7c7d">// Compare To What (Match Condition 7)</span> 1525 <span style="color:#7a7c7d">//</span> 1526 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dcr7 <span style="color:#2980b9">or</span> id_pc <span style="color:#2980b9">or</span> dcpu_adr_i <span style="color:#2980b9">or</span> dcpu_dat_dc 1527 <span style="color:#2980b9">or</span> dcpu_dat_lsu <span style="color:#2980b9">or</span> dcpu_we_i<span style="color:#3f8058">)</span> 1528 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dcr7<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CT</span><span style="color:#3f8058">])</span> <span style="color:#7a7c7d">// synopsys parallel_case</span> 1529 <span style="color:#f67400">3'b001</span><span style="color:#3f8058">:</span> match_cond7_ct <span style="color:#3f8058">=</span> id_pc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// insn fetch EA</span> 1530 <span style="color:#f67400">3'b010</span><span style="color:#3f8058">:</span> match_cond7_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load EA</span> 1531 <span style="color:#f67400">3'b011</span><span style="color:#3f8058">:</span> match_cond7_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// store EA</span> 1532 <span style="color:#f67400">3'b100</span><span style="color:#3f8058">:</span> match_cond7_ct <span style="color:#3f8058">=</span> dcpu_dat_dc<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load data</span> 1533 <span style="color:#f67400">3'b101</span><span style="color:#3f8058">:</span> match_cond7_ct <span style="color:#3f8058">=</span> dcpu_dat_lsu<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// store data</span> 1534 <span style="color:#f67400">3'b110</span><span style="color:#3f8058">:</span> match_cond7_ct <span style="color:#3f8058">=</span> dcpu_adr_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// load/store EA</span> 1535 <span style="font-weight:bold">default</span><span style="color:#3f8058">:</span>match_cond7_ct <span style="color:#3f8058">=</span> dcpu_we_i <span style="color:#3f8058">?</span> dcpu_dat_lsu <span style="color:#3f8058">:</span> dcpu_dat_dc<span style="color:#3f8058">;</span> 1536 <span style="font-weight:bold">endcase</span> 1537 1538 <span style="color:#7a7c7d">//</span> 1539 <span style="color:#7a7c7d">// When To Compare (Match Condition 7)</span> 1540 <span style="color:#7a7c7d">//</span> 1541 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dcr7 <span style="color:#2980b9">or</span> dcpu_cycstb_i<span style="color:#3f8058">)</span> 1542 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dcr7<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CT</span><span style="color:#3f8058">])</span> <span style="color:#7a7c7d">// synopsys parallel_case</span> 1543 <span style="color:#f67400">3'b000</span><span style="color:#3f8058">:</span> match_cond7_stb <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> <span style="color:#7a7c7d">//comparison disabled</span> 1544 <span style="color:#f67400">3'b001</span><span style="color:#3f8058">:</span> match_cond7_stb <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// insn fetch EA</span> 1545 <span style="font-weight:bold">default</span><span style="color:#3f8058">:</span>match_cond7_stb <span style="color:#3f8058">=</span> dcpu_cycstb_i<span style="color:#3f8058">;</span> <span style="color:#7a7c7d">// any load/store</span> 1546 <span style="font-weight:bold">endcase</span> 1547 1548 <span style="color:#7a7c7d">//</span> 1549 <span style="color:#7a7c7d">// Match Condition 7</span> 1550 <span style="color:#7a7c7d">//</span> 1551 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>match_cond7_stb <span style="color:#2980b9">or</span> dcr7 <span style="color:#2980b9">or</span> dvr7 <span style="color:#2980b9">or</span> match_cond7_ct<span style="color:#3f8058">)</span> 1552 <span style="font-weight:bold">casex</span> <span style="color:#3f8058">({</span>match_cond7_stb<span style="color:#3f8058">,</span> dcr7<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_CC</span><span style="color:#3f8058">]})</span> 1553 <span style="color:#f67400">4'b0_xxx</span><span style="color:#3f8058">,</span> 1554 <span style="color:#f67400">4'b1_000</span><span style="color:#3f8058">,</span> 1555 <span style="color:#f67400">4'b1_111</span><span style="color:#3f8058">:</span> match7 <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1556 <span style="color:#f67400">4'b1_001</span><span style="color:#3f8058">:</span> match7 <span style="color:#3f8058">=</span> 1557 <span style="color:#3f8058">({(</span>match_cond7_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr7<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond7_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">==</span> 1558 <span style="color:#3f8058">{(</span>dvr7<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr7<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr7<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1559 <span style="color:#f67400">4'b1_010</span><span style="color:#3f8058">:</span> match7 <span style="color:#3f8058">=</span> 1560 <span style="color:#3f8058">({(</span>match_cond7_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr7<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond7_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058"><</span> 1561 <span style="color:#3f8058">{(</span>dvr7<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr7<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr7<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1562 <span style="color:#f67400">4'b1_011</span><span style="color:#3f8058">:</span> match7 <span style="color:#3f8058">=</span> 1563 <span style="color:#3f8058">({(</span>match_cond7_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr7<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond7_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058"><=</span> 1564 <span style="color:#3f8058">{(</span>dvr7<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr7<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr7<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1565 <span style="color:#f67400">4'b1_100</span><span style="color:#3f8058">:</span> match7 <span style="color:#3f8058">=</span> 1566 <span style="color:#3f8058">({(</span>match_cond7_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr7<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond7_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">></span> 1567 <span style="color:#3f8058">{(</span>dvr7<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr7<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr7<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1568 <span style="color:#f67400">4'b1_101</span><span style="color:#3f8058">:</span> match7 <span style="color:#3f8058">=</span> 1569 <span style="color:#3f8058">({(</span>match_cond7_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr7<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond7_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">>=</span> 1570 <span style="color:#3f8058">{(</span>dvr7<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr7<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr7<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1571 <span style="color:#f67400">4'b1_110</span><span style="color:#3f8058">:</span> match7 <span style="color:#3f8058">=</span> 1572 <span style="color:#3f8058">({(</span>match_cond7_ct<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr7<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> match_cond7_ct<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]}</span> <span style="color:#3f8058">!=</span> 1573 <span style="color:#3f8058">{(</span>dvr7<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">^</span> dcr7<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DCR_SC</span><span style="color:#3f8058">]),</span> dvr7<span style="color:#3f8058">[</span><span style="color:#f67400">30</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]});</span> 1574 <span style="font-weight:bold">endcase</span> 1575 1576 <span style="color:#7a7c7d">//</span> 1577 <span style="color:#7a7c7d">// Watchpoint 7</span> 1578 <span style="color:#7a7c7d">//</span> 1579 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dmr1 <span style="color:#2980b9">or</span> match7 <span style="color:#2980b9">or</span> wp<span style="color:#3f8058">)</span> 1580 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dmr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DMR1_CW7</span><span style="color:#3f8058">])</span> 1581 <span style="color:#f67400">2'b00</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match7<span style="color:#3f8058">;</span> 1582 <span style="color:#f67400">2'b01</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match7 <span style="color:#3f8058">&</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">6</span><span style="color:#3f8058">];</span> 1583 <span style="color:#f67400">2'b10</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> match7 <span style="color:#3f8058">|</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">6</span><span style="color:#3f8058">];</span> 1584 <span style="color:#f67400">2'b11</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1585 <span style="font-weight:bold">endcase</span> 1586 1587 <span style="color:#7a7c7d">//</span> 1588 <span style="color:#7a7c7d">// Increment Watchpoint Counter 0</span> 1589 <span style="color:#7a7c7d">//</span> 1590 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>wp <span style="color:#2980b9">or</span> dmr2<span style="color:#3f8058">)</span> 1591 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dmr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DMR2_WCE0</span><span style="color:#3f8058">])</span> 1592 incr_wpcntr0 <span style="color:#3f8058">=</span> <span style="color:#3f8058">|(</span>wp <span style="color:#3f8058">&</span> <span style="color:#3f8058">~</span>dmr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DMR2_AWTC</span><span style="color:#3f8058">]);</span> 1593 <span style="font-weight:bold">else</span> 1594 incr_wpcntr0 <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1595 1596 <span style="color:#7a7c7d">//</span> 1597 <span style="color:#7a7c7d">// Match Condition Watchpoint Counter 0</span> 1598 <span style="color:#7a7c7d">//</span> 1599 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dwcr0<span style="color:#3f8058">)</span> 1600 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dwcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DWCR_MATCH</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> dwcr0<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DWCR_COUNT</span><span style="color:#3f8058">])</span> 1601 wpcntr0_match <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> 1602 <span style="font-weight:bold">else</span> 1603 wpcntr0_match <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1604 1605 1606 <span style="color:#7a7c7d">//</span> 1607 <span style="color:#7a7c7d">// Watchpoint 8</span> 1608 <span style="color:#7a7c7d">//</span> 1609 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dmr1 <span style="color:#2980b9">or</span> wpcntr0_match <span style="color:#2980b9">or</span> wp<span style="color:#3f8058">)</span> 1610 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dmr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DMR1_CW8</span><span style="color:#3f8058">])</span> 1611 <span style="color:#f67400">2'b00</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">8</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> wpcntr0_match<span style="color:#3f8058">;</span> 1612 <span style="color:#f67400">2'b01</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">8</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> wpcntr0_match <span style="color:#3f8058">&</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">];</span> 1613 <span style="color:#f67400">2'b10</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">8</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> wpcntr0_match <span style="color:#3f8058">|</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">];</span> 1614 <span style="color:#f67400">2'b11</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">8</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1615 <span style="font-weight:bold">endcase</span> 1616 1617 1618 <span style="color:#7a7c7d">//</span> 1619 <span style="color:#7a7c7d">// Increment Watchpoint Counter 1</span> 1620 <span style="color:#7a7c7d">//</span> 1621 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>wp <span style="color:#2980b9">or</span> dmr2<span style="color:#3f8058">)</span> 1622 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dmr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DMR2_WCE1</span><span style="color:#3f8058">])</span> 1623 incr_wpcntr1 <span style="color:#3f8058">=</span> <span style="color:#3f8058">|(</span>wp <span style="color:#3f8058">&</span> dmr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DMR2_AWTC</span><span style="color:#3f8058">]);</span> 1624 <span style="font-weight:bold">else</span> 1625 incr_wpcntr1 <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1626 1627 <span style="color:#7a7c7d">//</span> 1628 <span style="color:#7a7c7d">// Match Condition Watchpoint Counter 1</span> 1629 <span style="color:#7a7c7d">//</span> 1630 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dwcr1<span style="color:#3f8058">)</span> 1631 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>dwcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DWCR_MATCH</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> dwcr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DWCR_COUNT</span><span style="color:#3f8058">])</span> 1632 wpcntr1_match <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> 1633 <span style="font-weight:bold">else</span> 1634 wpcntr1_match <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1635 1636 <span style="color:#7a7c7d">//</span> 1637 <span style="color:#7a7c7d">// Watchpoint 9</span> 1638 <span style="color:#7a7c7d">//</span> 1639 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dmr1 <span style="color:#2980b9">or</span> wpcntr1_match <span style="color:#2980b9">or</span> wp<span style="color:#3f8058">)</span> 1640 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dmr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DMR1_CW9</span><span style="color:#3f8058">])</span> 1641 <span style="color:#f67400">2'b00</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">9</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> wpcntr1_match<span style="color:#3f8058">;</span> 1642 <span style="color:#f67400">2'b01</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">9</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> wpcntr1_match <span style="color:#3f8058">&</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">8</span><span style="color:#3f8058">];</span> 1643 <span style="color:#f67400">2'b10</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">9</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> wpcntr1_match <span style="color:#3f8058">|</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">8</span><span style="color:#3f8058">];</span> 1644 <span style="color:#f67400">2'b11</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">9</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1645 <span style="font-weight:bold">endcase</span> 1646 1647 <span style="color:#7a7c7d">//</span> 1648 <span style="color:#7a7c7d">// Watchpoint 10</span> 1649 <span style="color:#7a7c7d">//</span> 1650 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span>dmr1 <span style="color:#2980b9">or</span> dbg_ewt_i <span style="color:#2980b9">or</span> wp<span style="color:#3f8058">)</span> 1651 <span style="font-weight:bold">case</span> <span style="color:#3f8058">(</span>dmr1<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DMR1_CW10</span><span style="color:#3f8058">])</span> 1652 <span style="color:#f67400">2'b00</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">10</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> dbg_ewt_i<span style="color:#3f8058">;</span> 1653 <span style="color:#f67400">2'b01</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">10</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> dbg_ewt_i <span style="color:#3f8058">&</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">9</span><span style="color:#3f8058">];</span> 1654 <span style="color:#f67400">2'b10</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">10</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> dbg_ewt_i <span style="color:#3f8058">|</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">9</span><span style="color:#3f8058">];</span> 1655 <span style="color:#f67400">2'b11</span><span style="color:#3f8058">:</span> wp<span style="color:#3f8058">[</span><span style="color:#f67400">10</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1656 <span style="font-weight:bold">endcase</span> 1657 1658 <span style="color:#27ae60">`endif</span> 1659 1660 <span style="color:#7a7c7d">//</span> 1661 <span style="color:#7a7c7d">// Watchpoints can cause trap exception</span> 1662 <span style="color:#7a7c7d">//</span> 1663 <span style="color:#27ae60">`ifdef OR1200_DU_HWBKPTS</span> 1664 <span style="font-weight:bold">assign</span> du_hwbkpt <span style="color:#3f8058">=</span> <span style="color:#3f8058">|(</span>wp <span style="color:#3f8058">&</span> dmr2<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DMR2_WGB</span><span style="color:#3f8058">])</span> <span style="color:#3f8058">|</span> du_hwbkpt_hold <span style="color:#3f8058">|</span> <span style="color:#3f8058">(</span>dbg_bp_r <span style="color:#3f8058">&</span> <span style="color:#3f8058">~</span>dsr<span style="color:#3f8058">[</span><span style="color:#27ae60">`OR1200_DU_DSR_TE</span><span style="color:#3f8058">]);</span> 1665 <span style="color:#27ae60">`else</span> 1666 <span style="font-weight:bold">assign</span> du_hwbkpt <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1667 <span style="color:#27ae60">`endif</span> 1668 1669 <span style="color:#7a7c7d">// Hold du_hwbkpt if ex_freeze is active in order to cause trap exception </span> 1670 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 1671 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 1672 du_hwbkpt_hold <span style="color:#3f8058"><=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1673 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>du_hwbkpt <span style="color:#3f8058">&</span> ex_freeze<span style="color:#3f8058">)</span> 1674 du_hwbkpt_hold <span style="color:#3f8058"><=</span> <span style="color:#f67400">1'b1</span><span style="color:#3f8058">;</span> 1675 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(!</span>ex_freeze<span style="color:#3f8058">)</span> 1676 du_hwbkpt_hold <span style="color:#3f8058"><=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1677 1678 <span style="color:#27ae60">`ifdef OR1200_DU_TB_IMPLEMENTED</span> 1679 <span style="color:#7a7c7d">//</span> 1680 <span style="color:#7a7c7d">// Simple trace buffer</span> 1681 <span style="color:#7a7c7d">// (right now hardcoded for Xilinx Virtex FPGAs)</span> 1682 <span style="color:#7a7c7d">//</span> 1683 <span style="color:#7a7c7d">// Stores last 256 instruction addresses, instruction</span> 1684 <span style="color:#7a7c7d">// machine words and ALU results</span> 1685 <span style="color:#7a7c7d">//</span> 1686 1687 <span style="color:#7a7c7d">//</span> 1688 <span style="color:#7a7c7d">// Trace buffer write enable</span> 1689 <span style="color:#7a7c7d">//</span> 1690 <span style="font-weight:bold">assign</span> tb_enw <span style="color:#3f8058">=</span> <span style="color:#3f8058">~</span>ex_freeze <span style="color:#3f8058">&</span> <span style="color:#3f8058">~((</span>ex_insn<span style="color:#3f8058">[</span><span style="color:#f67400">31</span><span style="color:#3f8058">:</span><span style="color:#f67400">26</span><span style="color:#3f8058">]</span> <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_OR32_NOP</span><span style="color:#3f8058">)</span> <span style="color:#3f8058">&</span> ex_insn<span style="color:#3f8058">[</span><span style="color:#f67400">16</span><span style="color:#3f8058">]);</span> 1691 1692 <span style="color:#7a7c7d">//</span> 1693 <span style="color:#7a7c7d">// Trace buffer write address pointer</span> 1694 <span style="color:#7a7c7d">//</span> 1695 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 1696 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 1697 tb_wadr <span style="color:#3f8058"><=</span> <span style="color:#f67400">8'h00</span><span style="color:#3f8058">;</span> 1698 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>tb_enw<span style="color:#3f8058">)</span> 1699 tb_wadr <span style="color:#3f8058"><=</span> tb_wadr <span style="color:#3f8058">+</span> <span style="color:#f67400">8'd1</span><span style="color:#3f8058">;</span> 1700 1701 <span style="color:#7a7c7d">//</span> 1702 <span style="color:#7a7c7d">// Free running counter (time stamp)</span> 1703 <span style="color:#7a7c7d">//</span> 1704 <span style="font-weight:bold">always</span> <span style="color:#3f8058">@(</span><span style="font-weight:bold">posedge</span> clk <span style="color:#2980b9">or</span> <span style="color:#27ae60">`OR1200_RST_EVENT</span> rst<span style="color:#3f8058">)</span> 1705 <span style="font-weight:bold">if</span> <span style="color:#3f8058">(</span>rst <span style="color:#3f8058">==</span> <span style="color:#27ae60">`OR1200_RST_VALUE</span><span style="color:#3f8058">)</span> 1706 tb_timstmp <span style="color:#3f8058"><=</span> <span style="color:#f67400">32'h00000000</span><span style="color:#3f8058">;</span> 1707 <span style="font-weight:bold">else</span> <span style="font-weight:bold">if</span> <span style="color:#3f8058">(!</span>dbg_bp_r<span style="color:#3f8058">)</span> 1708 tb_timstmp <span style="color:#3f8058"><=</span> tb_timstmp <span style="color:#3f8058">+</span> <span style="color:#f67400">32'd1</span><span style="color:#3f8058">;</span> 1709 1710 <span style="color:#7a7c7d">//</span> 1711 <span style="color:#7a7c7d">// Trace buffer RAMs</span> 1712 <span style="color:#7a7c7d">//</span> 1713 1714 or1200_dpram_256x32 tbia_ram<span style="color:#3f8058">(</span> 1715 .clk_a<span style="color:#3f8058">(</span>clk<span style="color:#3f8058">),</span> 1716 .rst_a<span style="color:#3f8058">(</span><span style="color:#f67400">1'b0</span><span style="color:#3f8058">),</span> 1717 .addr_a<span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]),</span> 1718 .ce_a<span style="color:#3f8058">(</span><span style="color:#f67400">1'b1</span><span style="color:#3f8058">),</span> 1719 .oe_a<span style="color:#3f8058">(</span><span style="color:#f67400">1'b1</span><span style="color:#3f8058">),</span> 1720 .do_a<span style="color:#3f8058">(</span>tbia_dat_o<span style="color:#3f8058">),</span> 1721 1722 .clk_b<span style="color:#3f8058">(</span>clk<span style="color:#3f8058">),</span> 1723 .rst_b<span style="color:#3f8058">(</span><span style="color:#f67400">1'b0</span><span style="color:#3f8058">),</span> 1724 .addr_b<span style="color:#3f8058">(</span>tb_wadr<span style="color:#3f8058">),</span> 1725 .di_b<span style="color:#3f8058">(</span>spr_dat_npc<span style="color:#3f8058">),</span> 1726 .ce_b<span style="color:#3f8058">(</span><span style="color:#f67400">1'b1</span><span style="color:#3f8058">),</span> 1727 .we_b<span style="color:#3f8058">(</span>tb_enw<span style="color:#3f8058">)</span> 1728 1729 <span style="color:#3f8058">);</span> 1730 1731 or1200_dpram_256x32 tbim_ram<span style="color:#3f8058">(</span> 1732 .clk_a<span style="color:#3f8058">(</span>clk<span style="color:#3f8058">),</span> 1733 .rst_a<span style="color:#3f8058">(</span><span style="color:#f67400">1'b0</span><span style="color:#3f8058">),</span> 1734 .addr_a<span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]),</span> 1735 .ce_a<span style="color:#3f8058">(</span><span style="color:#f67400">1'b1</span><span style="color:#3f8058">),</span> 1736 .oe_a<span style="color:#3f8058">(</span><span style="color:#f67400">1'b1</span><span style="color:#3f8058">),</span> 1737 .do_a<span style="color:#3f8058">(</span>tbim_dat_o<span style="color:#3f8058">),</span> 1738 1739 .clk_b<span style="color:#3f8058">(</span>clk<span style="color:#3f8058">),</span> 1740 .rst_b<span style="color:#3f8058">(</span><span style="color:#f67400">1'b0</span><span style="color:#3f8058">),</span> 1741 .addr_b<span style="color:#3f8058">(</span>tb_wadr<span style="color:#3f8058">),</span> 1742 .di_b<span style="color:#3f8058">(</span>ex_insn<span style="color:#3f8058">),</span> 1743 .ce_b<span style="color:#3f8058">(</span><span style="color:#f67400">1'b1</span><span style="color:#3f8058">),</span> 1744 .we_b<span style="color:#3f8058">(</span>tb_enw<span style="color:#3f8058">)</span> 1745 <span style="color:#3f8058">);</span> 1746 1747 or1200_dpram_256x32 tbar_ram<span style="color:#3f8058">(</span> 1748 .clk_a<span style="color:#3f8058">(</span>clk<span style="color:#3f8058">),</span> 1749 .rst_a<span style="color:#3f8058">(</span><span style="color:#f67400">1'b0</span><span style="color:#3f8058">),</span> 1750 .addr_a<span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]),</span> 1751 .ce_a<span style="color:#3f8058">(</span><span style="color:#f67400">1'b1</span><span style="color:#3f8058">),</span> 1752 .oe_a<span style="color:#3f8058">(</span><span style="color:#f67400">1'b1</span><span style="color:#3f8058">),</span> 1753 .do_a<span style="color:#3f8058">(</span>tbar_dat_o<span style="color:#3f8058">),</span> 1754 1755 .clk_b<span style="color:#3f8058">(</span>clk<span style="color:#3f8058">),</span> 1756 .rst_b<span style="color:#3f8058">(</span><span style="color:#f67400">1'b0</span><span style="color:#3f8058">),</span> 1757 .addr_b<span style="color:#3f8058">(</span>tb_wadr<span style="color:#3f8058">),</span> 1758 .di_b<span style="color:#3f8058">(</span>rf_dataw<span style="color:#3f8058">),</span> 1759 .ce_b<span style="color:#3f8058">(</span><span style="color:#f67400">1'b1</span><span style="color:#3f8058">),</span> 1760 .we_b<span style="color:#3f8058">(</span>tb_enw<span style="color:#3f8058">)</span> 1761 <span style="color:#3f8058">);</span> 1762 1763 or1200_dpram_256x32 tbts_ram<span style="color:#3f8058">(</span> 1764 .clk_a<span style="color:#3f8058">(</span>clk<span style="color:#3f8058">),</span> 1765 .rst_a<span style="color:#3f8058">(</span><span style="color:#f67400">1'b0</span><span style="color:#3f8058">),</span> 1766 .addr_a<span style="color:#3f8058">(</span>spr_addr<span style="color:#3f8058">[</span><span style="color:#f67400">7</span><span style="color:#3f8058">:</span><span style="color:#f67400">0</span><span style="color:#3f8058">]),</span> 1767 .ce_a<span style="color:#3f8058">(</span><span style="color:#f67400">1'b1</span><span style="color:#3f8058">),</span> 1768 .oe_a<span style="color:#3f8058">(</span><span style="color:#f67400">1'b1</span><span style="color:#3f8058">),</span> 1769 .do_a<span style="color:#3f8058">(</span>tbts_dat_o<span style="color:#3f8058">),</span> 1770 1771 .clk_b<span style="color:#3f8058">(</span>clk<span style="color:#3f8058">),</span> 1772 .rst_b<span style="color:#3f8058">(</span><span style="color:#f67400">1'b0</span><span style="color:#3f8058">),</span> 1773 .addr_b<span style="color:#3f8058">(</span>tb_wadr<span style="color:#3f8058">),</span> 1774 .di_b<span style="color:#3f8058">(</span>tb_timstmp<span style="color:#3f8058">),</span> 1775 .ce_b<span style="color:#3f8058">(</span><span style="color:#f67400">1'b1</span><span style="color:#3f8058">),</span> 1776 .we_b<span style="color:#3f8058">(</span>tb_enw<span style="color:#3f8058">)</span> 1777 <span style="color:#3f8058">);</span> 1778 1779 <span style="color:#27ae60">`else</span> 1780 1781 <span style="font-weight:bold">assign</span> tbia_dat_o <span style="color:#3f8058">=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 1782 <span style="font-weight:bold">assign</span> tbim_dat_o <span style="color:#3f8058">=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 1783 <span style="font-weight:bold">assign</span> tbar_dat_o <span style="color:#3f8058">=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 1784 <span style="font-weight:bold">assign</span> tbts_dat_o <span style="color:#3f8058">=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 1785 1786 <span style="color:#27ae60">`endif </span><span style="color:#7a7c7d">// OR1200_DU_TB_IMPLEMENTED</span> 1787 1788 <span style="color:#27ae60">`else </span><span style="color:#7a7c7d">// OR1200_DU_IMPLEMENTED</span> 1789 1790 <span style="color:#7a7c7d">//</span> 1791 <span style="color:#7a7c7d">// When DU is not implemented, drive all outputs as would when DU is disabled</span> 1792 <span style="color:#7a7c7d">//</span> 1793 <span style="font-weight:bold">assign</span> dbg_bp_o <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1794 <span style="font-weight:bold">assign</span> du_dsr <span style="color:#3f8058">=</span> <span style="color:#3f8058">{</span><span style="color:#27ae60">`OR1200_DU_DSR_WIDTH</span><span style="color:#3f8058">{</span><span style="color:#f67400">1'b0</span><span style="color:#3f8058">}};</span> 1795 <span style="font-weight:bold">assign</span> du_dmr1 <span style="color:#3f8058">=</span> <span style="color:#3f8058">{</span><span style="color:#f67400">25</span><span style="color:#3f8058">{</span><span style="color:#f67400">1'b0</span><span style="color:#3f8058">}};</span> 1796 <span style="font-weight:bold">assign</span> du_hwbkpt <span style="color:#3f8058">=</span> <span style="color:#f67400">1'b0</span><span style="color:#3f8058">;</span> 1797 1798 <span style="color:#7a7c7d">//</span> 1799 <span style="color:#7a7c7d">// Read DU registers</span> 1800 <span style="color:#7a7c7d">//</span> 1801 <span style="color:#27ae60">`ifdef OR1200_DU_READREGS</span> 1802 <span style="font-weight:bold">assign</span> spr_dat_o <span style="color:#3f8058">=</span> <span style="color:#f67400">32'h0000_0000</span><span style="color:#3f8058">;</span> 1803 <span style="color:#27ae60">`ifdef OR1200_DU_UNUSED_ZERO</span> 1804 <span style="color:#27ae60">`endif</span> 1805 <span style="color:#27ae60">`endif</span> 1806 1807 <span style="color:#27ae60">`endif</span> 1808 1809 <span style="font-weight:bold">endmodule</span> 1810 </pre></body></html>